LP61L1024U-12 datasheet(11/16 Pages) AMICC

Part #	LP61L1024U-12

Description	128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM

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Manufacturer	AMICC [AMIC Technology]

Direct Link	http://www.amictechnology.com

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LP61L1024

(August, 2002, Version 2.1)

10

AMIC Technology, Inc.

AC Test Conditions

Input Pulse Levels

0V to 3.0V

Input Rise and Fall Time

3 ns

Input and Output Timing Reference Levels

1.5V

Output Load

See Figures 1 and 2

+3.3V

I/O

350Ω

320Ω

30pF*

* Including scope and jig.

+3.3V

I/O

350Ω

320Ω

5pF*

* Including scope and jig.

Figure 1. Output Load

Figure 2. Output Load for tCLZ1,

tCLZ2, tOHZ, tOLZ, tCHZ1,

tCHZ2, tWHZ, and tOW

Data Retention Characteristics (TA = 0

°C to 70°C)

Symbol

Parameter

Min.

Max.

Unit

Conditions

VDR1

VCC for Data Retention

2

3.6

V

CE1

≥ VCC - 0.2V

CE2

≥ VCC - 0.2V or

CE2

≤ 0.2V

VDR2

2

3.6

V

CE2

≤ 0.2V

CE1

≥ VCC - 0.2V or

CE1

≤ 0.2V

ICCDR1

Data Retention Current

-

5

mA

VCC = 3.0V

CE1

≥ VCC - 0.2V

CE2

≥ VCC - 0.2V

VIN

≥ VCC - 0.2V or

VIN

≤ 0.2V

ICCDR2

-

5

mA

VCC = 3.0V

CE2

≤ 0.2V

CE1

≤ 0.2V

VIN

≥ VCC - 0.2V or

VIN

≤ 0.2V

tCDR

Chip Disable to Data Retention Time

0

-

ns

See Retention Waveform

tR

Operation Recovery Time

5

-

ms

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LP61L1024U-12 Datasheet(PDF) 11 Page - AMIC Technology

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