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LS7213R Datasheet(PDF) 4 Page - LSI Computer Systems |
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LS7213R Datasheet(HTML) 4 Page - LSI Computer Systems |
4 / 5 page 7213R-120205-4 A B D C E F G H OUT1(DLD) OUT1(OFD) OUT1(OND) OUT1(OST) RESET TRIG A. Turn-on delay in OND and DLD modes; Pulse-width in OST mode. B. Turn-off delay in OFD and DLD modes. C. Pulse-width extended by re-trigger in OST mode. No effect in OND and DLD modes because TRIG switches back low before turn-on delay has timed out. D. Turn-off delay in OFD mode. FIGURE 3. MODE ILLUSTRATION WITH TRIG, OUT1 AND RESET E. Turn-on delay in OND and DLD modes; pulse-width in OST mode. F. No effect in OND, OFD and DLD modes because of Trig’s switching back to opposite levels. G. Time-out aborted and OUT1 forced high by RESET. H. After the removal of RESET, OUT1 switches to the inverse polarity of TRIG immediately (OFD) or after the timeout (OND, DLD). No effect in OST. The table below shows the delays obtained with the following components R1 = 56k Ω, R2 = 500kΩ and C2 = 0.002µF. At any scale factor, the delay changes from minimum to maximum as the potentiometer, R2 is varied from minimum to maximum. D3 D2 D1 TIMING RANGE 0 0 0 0.1 sec - 1 sec. 0 0 1 1 sec. - 10 sec. 0 1 0 10 sec - 100 sec. 0 1 1 0.1 min. to 1 min. 1 0 0 1 min. - 10 min 1 0 1 10 min. - 100 min. 1 1 0 0.1 hr. - 1 hr. 1 1 1 1 hr. - 10 hr. C1 = 0.22µF, produces flash pulses of 0.1 sec duration at Out2 LATCH LATCH LATCH LATCH LATCH D3 D2 D1 RC A TRIGGER RANGE DECODER TIMER OSC CONTROL LOGIC POR GENERATOR OUTPUT DRIVER OUT1 OUT2 LATCH B LATCH FLASHEN FIGURE 2. LS7213R BLOCK DIAGRAM 1 2 3 10 4 5 6 8 +V -V 14 VDD 7 Vss OUTPUT DRIVER OSC CAP 9 13 12 RESET 11 1 2 3 4 5 7 6 D3 D2 D1 A B FLASHEN Vss (-V) V DD (+V) 14 OUT1 13 OUT2 12 RESET 11 RC 10 CAP 9 8 RESET INPUT FIGURE 4. TYPICAL APPLICATION WITH OUT1 AS RELAY DRIVE AND OUT2 AS FLASHER TRIGGER INPUT LS7213R +5V LED C2 C1 300 R1 R2 TRIGGER |
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