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W947D2CBJX5G Datasheet(PDF) 6 Page - Winbond |
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W947D2CBJX5G Datasheet(HTML) 6 Page - Winbond |
6 / 65 page W989D6CB / W989D2CB 512Mb Mobile LPSDR Publication Release Date : August 07, 2013 - 6 - Revision : A01-006 5. PIN DESCRIPTION 5.1 Signal Description Ball Name Function Description A [n : 0] Address Multiplexed pins for row and column address. A10 is Auto Precharge Select BA0, BA1 Bank Select Select bank to activate during row address latch time, or bank to read/write during address latch time. DQ0~DQ15 (×16) DQ0~DQ31 (×32) Data Input/ Output Multiplexed pins for data output and input. CS Chip Select Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues. RAS Row Address Strobe Command input. When sampled at the rising edge of the clock, RAS , CAS and WE define the operation to be executed. CAS Column Address Strobe Referred to RAS WE Write Enable Referred to WE UDQM / LDQM(x16) DQM0 ~ DQM3 (x32) I/O Mask The output buffer is placed at Hi-Z (with latency of 2 in CL=2, 3;) when DQM is sampled high in read cycle. In write cycle, sampling DQM high will block the write operation with zero latency. CLK Clock Inputs System clock used to sample inputs on the rising edge of clock. CKE Clock Enable CKE controls the clock activation and deactivation. When CKE is low, Power Down mode, Suspend mode or Self Refresh mode is entered. VDD Power Power supply for input buffers and logic circuit inside DRAM. VSS Ground Ground for input buffers and logic circuit inside DRAM. VDDQ Power for I/O Buffer Power supply separated from VDD, used for output buffers to improve noise. VSSQ Ground for I/O Buffer Separated ground from VSS, used for output buffers to improve noise. NC No Connection No connection 5.2 Addressing Table Item 512 Mb Number of banks 4 Bank address pins BA0,BA1 Auto precharge pin A10/AP X16 Row addresses A0-A12 Column addresses A0-A9 x32 Row addresses A0-A12 Column addresses A0-A8 |
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