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PALCE20V8H-20JC Datasheet(PDF) 4 Page - Advanced Micro Devices |
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PALCE20V8H-20JC Datasheet(HTML) 4 Page - Advanced Micro Devices |
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4 / 16 page  AMD 2-158 PALCE20V8 Family FUNCTIONAL DESCRIPTION The PALCE20V8 is a universal PAL device. It has eight independently configurable macrocells (MC0..MC7). Each macrocell can be configured as a registered out- put, combinatorial output, combinatorial I/O, or dedi- cated input. The programming matrix implements a programmable AND logic array, which drives a fixed OR logic array. Buffers for device inputs have complemen- tary outputs to provide user-programmable input signal polarity. Pins 1 and 13 serve either as array inputs or as clock (CLK) and output enable ( OE) for all flip-flops. Unused input pins should be tied directly to VCC or GND. Product terms with all bits unprogrammed (discon- nected) assume the logical HIGH state and product terms with both true and complement of any input signal connected assume a logical LOW state. The programmable functions on the PALCE20V8 are automatically configured from the user’s design specifi- cation, which can be in a number of formats. The design specification is processed by development software to verify the design and create a programming file. This file, once downloaded to a programmer, configures the device according to the user’s desired function. The user is given two design options with the PALCE20V8. First, it can be programmed as an emu- lated PAL device. This includes the PAL20R8 series and most 24-pin combinatorial PAL devices. The PAL device programmer manufacturer will supply device codes for the standard PAL architectures to be used with the PALCE20V8. The programmer will program the PALCE20V8 to the corresponding PAL device architec- ture. This allows the user to use existing standard PAL device JEDEC files without making any changes to them. Alternatively, the device can be programmed directly as a PALCE20V8. Here the user must use the PALCE20V8 device code. This option provides full utili- zation of the macrocells, allowing non-standard archi- tectures to be built. 16491D-4 * In Macrocells MC0 and MC7, SG1 is replaced by SG0 on the feedback multiplexer. 11 0X 10 11 10 00 01 11 10 0X 10 0X 11 SG1 SL1X CLK OE VCC To Adjacent Macrocell From Adjacent Pin SL0X *SG1 I/OX DQ Q SL0X Figure 1. PALCE20V8 Macrocell |
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