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W9825G6JB-6 Datasheet(PDF) 5 Page - Winbond |
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W9825G6JB-6 Datasheet(HTML) 5 Page - Winbond |
5 / 42 page W9825G6JB Publication Release Date: Oct. 15, 2013 - 5 - Revision A04 5. BALL DESCRIPTION BALL LOCATION BALL NAME FUNCTION DESCRIPTION H7, H8, J8, J7, J3, J2, H3, H2, H1, G3, H9, G2, G1 A0 A12 Address Multiplexed pins for row and column address. Row address: A0 A12. Column address: A0A8. A10 is sampled during a precharge command to determine if all banks are to be precharged or bank selected by BS0, BS1. G7, G8 BS0, BS1 Bank Select Select bank to activate during row address latch time, or bank to read/write during address latch time. A8, B9, B8, C9, C8, D9, D8, E9, E1, D2, D1, C2, C1, B2, B1, A2 DQ0 DQ15 Data Input/ Output Multiplexed pins for data output and input. G9 CS Chip Select Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues. F8 RAS Row Address Strobe Command input. When sampled at the rising edge of the clock RAS , CAS and WE define the operation to be executed. F7 CAS Column Address Strobe Referred to RAS F9 WE Write Enable Referred to RAS F1, E8 UDQM, LDQM Input/output mask The output buffer is placed at Hi-Z (with latency of 2) when DQM is sampled high in read cycle. In write cycle, sampling DQM high will block the write operation with zero latency. F2 CLK Clock Inputs System clock used to sample inputs on the rising edge of clock. F3 CKE Clock Enable CKE controls the clock activation and deactivation. When CKE is low, Power Down mode, Suspend mode, or Self Refresh mode is entered. A9, E7, J9 VDD Power Power for input buffers and logic circuit inside DRAM. A1, E3, J1 VSS Ground Ground for input buffers and logic circuit inside DRAM. A7, B3, C7, D3 VDDQ Power for I/O buffer Separated power from VDD, to improve DQ noise immunity. A3, B7, C3, D7 VSSQ Ground for I/O buffer Separated ground from VSS, to improve DQ noise immunity. E2 NC No Connection No connection |
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