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W988D6FBGX6I Datasheet(PDF) 4 Page - Winbond |
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W988D6FBGX6I Datasheet(HTML) 4 Page - Winbond |
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4 / 66 page  W988D6FB / W988D2FB 256Mb Mobile LPSDR Publication Release Date : August 15, 2013 - 4 - Revision A01-004 8.1.21 Data Write/Output Enable, Data Mask/Output Disable Command ........................................................ 23 9.OPERATION............................................................................................................................... 23 9.1 Read Operation.................................................................................................................................23 9.2 Write Operation .................................................................................................................................23 9.3 Precharge .........................................................................................................................................24 9.3.1 Auto Precharge ........................................................................................................................................ 24 9.3.2 READ with auto precharge interrupted by a READ (with or without auto precharge) ............................. 24 9.3.3 READ with auto precharge interrupted by a WRITE (with or without auto precharge)............................ 25 9.3.4 WRITE with auto precharge interrupted by a READ (with or without auto precharge)............................ 25 9.3.5 WRITE with auto precharge interrupted by a WRITE (with or without auto precharge) .......................... 26 9.4 Burst Termination..............................................................................................................................26 9.5 Mode Register Operation ..................................................................................................................27 9.5.1 Burst Length field (A2~A0) ....................................................................................................................... 27 9.5.2 Addressing Mode Select (A3) .................................................................................................................. 27 9.5.3 Addressing Sequence for Sequential Mode............................................................................................. 28 9.5.4 Addressing Sequence for Interleave Mode .............................................................................................. 28 9.5.5 Addressing Sequence Example (Burst Length = 8 and Input Address is 13).......................................... 29 9.5.6 Read Cycle CAS Latency = 3 ............................................................................................................... 29 9.5.7 CAS Latency field (A6~A4) ................................................................................................................... 30 9.5.8 Mode Register Definition .......................................................................................................................... 30 9.6 Extended Mode Register Description................................................................................................31 9.7 Simplified State Diagram...................................................................................................................32 10. CONTROL TIMING WAVEFORMS ......................................................................................... 33 10.1 Command Input Timing...................................................................................................................33 10.2 Read Timing....................................................................................................................................34 10.3 Control Timing of Input Data (x16) ..................................................................................................35 10.4 Control Timing of Output Data (x16) ...............................................................................................36 10.5 Control Timing of Input Data (x32) ..................................................................................................37 10.6 Control Timing of Output Data (x32) ...............................................................................................38 10.7 Mode register Set (MRS) Cycle ......................................................................................................39 10.8 Extended Mode register Set (EMRS) Cycle....................................................................................40 11. OPERATING TIMING EXAMPLE ............................................................................................ 41 11.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) ........................................................41 11.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto Precharge) ...........................42 11.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) ......................................................43 11.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto Precharge) ...........................44 11.5 Interleaved Bank Write (Burst Length = 8) ......................................................................................45 11.6 Interleaved Bank Write (Burst Length = 8, Auto Precharge) ...........................................................46 11.7 Page Mode Read (Burst Length = 4, CAS Latency = 3) ...............................................................47 11.8 Page Mode Read / Write (Burst Length = 8, CAS Latency = 3)....................................................48 11.9 Auto Precharge Read (Burst Length = 4, CAS Latency = 3) ........................................................49 |
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