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W25X05CLSNIG Datasheet(PDF) 9 Page - Winbond |
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W25X05CLSNIG Datasheet(HTML) 9 Page - Winbond |
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9 / 51 page  W25X05CL/10CL/20CL Publication Release Date: March 23, 2012 - 9 - Revision B 7.2 WRITE PROTECTION Applications that use non-volatile memory must take into consideration the possibility of noise and other adverse system conditions that may compromise data integrity. To address this concern, the W25X05CL/10CL/20CL provide several means to protect data from inadvertent writes. 7.2.1 Write Protect Features Device resets when VCC is below threshold. Time delay write disable after Power-up. Write enable/disable instructions. Automatic write disable after program and erase. Software and Hardware (/WP pin) write protection using Status Register. Write Protection using Power-down instruction. Upon power-up or at power-down, the W25X05CL/10CL/20CL will maintain a reset condition while VCC is below the threshold value of VWI, (See Power-up Timing and Voltage Levels and Figure 26). While reset, all operations are disabled and no instructions are recognized. During power-up and after the VCC voltage exceeds VWI, all program and erase related instructions are further disabled for a time delay of tPUW. This includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the Write Status Register instructions. Note that the chip select pin (/CS) must track the VCC supply level at power-up until the VCC-min level and tVSL time delay is reached. If needed, a pull-up resister on /CS can be used to accomplish this. After power-up the device is automatically placed in a write-disabled state with the Status Register Write Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program, Sector Erase, Chip Erase or Write Status Register instruction will be accepted. After completing a program, erase or write instruction the Write Enable Latch (WEL) is automatically cleared to a write-disabled state of 0. Software controlled write protection is facilitated using the Write Status Register instruction and setting the Status Register Protect (SRP) and Block Protect (TB, BP1 and BP0) bits. These allow a portion small as 4KB sector or the entire memory array to be configured as read only. Used in conjunction with the Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under hardware control. See Status Register for further information. Additionally, the Power-down instruction offers an extra level of write protection as all instructions are ignored except for the Release Power- down instruction. |
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