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EDX1032BBBG-3C-F Datasheet(PDF) 1 Page - Elpida Memory |
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EDX1032BBBG-3C-F Datasheet(HTML) 1 Page - Elpida Memory |
1 / 85 page Doc. No. E1819E20 (Ver. 2.0) Date Published March 2012 (K) Japan Printed in Japan URL: http://www.elpida.com Elpida Memory, Inc. 2011-2012 Overview The EDX1032BBBG is 1G bits XDR™ DRAM organized as 32M words × 32 bits. They are general-purpose high-perfor- mance memory devices suitable for use in a broad range of applications. The use of Differential Rambus Signaling Level (DRSL) tech- nology permits 3200 Mb/s transfer rates for EDX1032BBBG, while using conventional system and board design technolo- gies. The EDX1032BBBG device is capable of sustained data trans- fers of 12800 MB/s. XDR DRAM device architecture allows the highest sustained bandwidth for multiple, interleaved randomly addressed mem- ory transactions. The highly-efficient protocol yields over 95% utilization while allowing fine access granularity. The device’s eight banks support up to four interleaved transactions. The EDX1032BBBG is packaged in 150-ball FBGA, compati- ble with Rambus XDR DRAM pin configuration. Features • Highest pin bandwidth available Octal Data Rate (ODR) Signaling, 3200 Mb/s • Bi-directional differential RSL (DRSL) - Flexible read/write bandwidth allocation - Minimum pin count • Programmable on-chip termination -Adaptive impedance matching -Reduced system cost and routing complexity • Low power PLL/DLL design • Highest sustained bandwidth per DRAM device • EDX1032BBBG:12800 MB/s sustained data rates • Eight banks: bank-interleaved transactions at full bandwidth • Dynamic request scheduling • Early-read-after-write support for maximum efficiency • Zero overhead refresh • Dynamic width control • EDX1032BBBG supports × 32, × 16, × 8 and × 4 mode •Low latency • 2.50 ns request packets • Point-to-point data interconnect for fastest possible flight time • Support for low-latency, fast-cycle cores •Low power • 1.5V VDD • Programmable small-swing I/O signaling (DRSL) • Low power PLL/DLL design • Powerdown self-refresh support • Per pin I/O powerdown for narrow-width operation 1G bits XDR DRAM EDX1032BBBG (32M words × 32 bits) DATA SHEET |
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