EVAL-ADV7614EB1Z datasheet(5/20 Pages) AD

Part #	EVAL-ADV7614EB1Z

Description	12-Bit Deep Color with Quad HDMI Receiver

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Data Sheet

ADV7614

Rev. C | Page 5 of 20

DATA AND I2C TIMING CHARACTERISTICS

DVDD = 1.8 V ± 5%, DVDDIO = 3.3 V ± 5%, PVDD = 1.8 V ± 5%, TVDD = 3.3 V ± 5%, CVDD = 1.8 V ± 5%, TMIN to TMAX = −40°C to

+70°C, unless otherwise noted.

Table 2.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

VIDEO SYSTEM CLOCK AND CRYSTAL

Crystal Nominal Frequency

24.576/28.6363

MHz

Crystal Frequency Stability

±50

ppm

LLC Frequency Range

12.825

170

MHz

External Clock Source 1

External crystal must operate at 1.8 V

Input High Voltage

VIH

Ball H15 (XTALP) driven with external

clock source

1.2

V

Input Low Voltage

VIL

Ball H15 (XTALP) driven with external

clock source

0.4

V

RESET FEATURE

Reset Pulse Width

5

ms

CLOCK OUTPUTS

LLC Mark Space Ratio

t9:t10

45:55

55:45

% duty

cycle

I2C PORTS (FAST MODE)

xCL Frequency2

400

kHz

xCL Minimum Pulse Width High2

t1

600

ns

xCL Minimum Pulse Width Low2

t2

1.3

µs

Hold Time (Start Condition)

t3

600

ns

Setup Time (Start Condition)

t4

600

ns

xDA Setup Time2

t5

100

ns

xCL and xDA Rise Time2

t6

300

ns

xCL and xDA Fall Time2

t7

300

ns

Setup Time (Stop Condition)

t8

0.6

µs

I2C PORTS (NORMAL MODE)

xCL Frequency2

100

kHz

xCL Minimum Pulse Width High2

t1

4.0

µs

xCL Minimum Pulse Width Low2

t2

4.7

µs

Hold Time (Start Condition)

t3

4.0

µs

Setup Time (Start Condition)

t4

4.7

µs

xDA Setup Time2

t5

250

ns

xCL and xDA Rise Time2

t6

1000

ns

xCL and xDA Fall Time2

t7

300

ns

Setup Time (Stop Condition)

t8

4.0

µs

DATA AND CONTROL OUTPUTS3

Data Output Transition Time SDR (CP)

t11

End of valid data to negative clock edge

0.55

ns

Data Output Transition Time SDR (CP)

t12

Negative clock edge to start of valid data

1.0

ns

VIDEO I2S PORT

Master Mode

SCLK Mark Space Ratio

t13:t14

45:55

55:45

% duty

cycle

LRCLK Data Transition Time

t15

End of valid data to negative SCLK edge

10

ns

LRCLK Data Transition Time

t16

Negative SCLK edge to start of valid data

10

ns

I2Sx Data Transition Time 4

t17

End of valid data to negative SCLK edge

5

ns

I2Sx Data Transition Time4

t18

Negative SCLK edge to start of valid data

5

ns

1

The XTAL_CTRL bit must be enabled for external oscillator operation. A 1.8 V oscillator must be used.

2

The prefix x refers to S, DDCA_S, DDCB_S, DDCC_S, and DDCD_S.

3

LLC DLL disabled.

4

The suffix x refers to 0, 1, 2, and 3.

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