ADN4661 datasheet(4/12 Pages) AD

Part #	ADN4661

Description	Single, 3 V, CMOS, LVDS, High Speed Differential Driver

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ADN4661

Rev. 0 | Page 4 of 12

AC CHARACTERISTICS

VCC = 3 V to 3.6 V; RL = 100 Ω; CL1 = 15 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.

Table 2.

Parameter2

Symbol

Min

Typ

Max

Unit

Conditions/Comments3, 4

Differential Propagation Delay High to Low

tPHLD

0.3

0.8

1.5

ns

See Figure 3 and Figure 4

Differential Propagation Delay Low to High

tPLHD

0.3

1.1

1.5

ns

See Figure 3 and Figure 4

Differential Pulse Skew |tPHLD − tPLHD|5

tSKD1

0

0.3

0.7

ns

See Figure 3 and Figure 4

Differential Part-to-Part Skew6

tSKD3

0

1.0

ns

See Figure 3 and Figure 4

Differential Part-to-Part Skew7

tSKD4

0

1.2

Ns

See Figure 3 and Figure 4

Rise Time

tTLH

0.2

0.5

1.0

ns

See Figure 3 and Figure 4

Fall Time

tTHL

0.2

0.5

1.0

ns

See Figure 3 and Figure 4

Maximum Operating Frequency8

fMAX

350

MHz

See Figure 3

1 CL includes probe and jig capacitance.

2 AC parameters are guaranteed by design and characterization.

3 Generator waveform for all tests, unless otherwise specified: f = 50 MHz, ZO = 50 Ω, tTLH ≤ 1 ns, and tTHL ≤ 1 ns.

4 All input voltages are for one channel unless otherwise specified. Other inputs are set to GND.

5 tSKD1 = |tPHLD − tPLHD| is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the

same channel.

6 tSKD3, differential part-to-part skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification

applies to devices at the same VCC and within 5°C of each other within the operating temperature range.

7 tSKD4, differential part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended

operating temperatures and voltage ranges, and across process distribution. tSKD4 is defined as |maximum − minimum| differential propagation delay.

8 fMAX generator input conditions: tTLH = tTHL < 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45% to 55%, VOD > 250 mV, all channels

switching.

Test Circuits and Timing Diagrams

RL/2

DIN

DOUT+

DOUT–

VCC

VOS

VOD

V

Figure 2. Test Circuit for Driver VOD and VOS

CL

DIN

DOUT+

DOUT–

NOTES

1. CL INCLUDES PROBE AND JIG CAPACITANCE.

SIGNAL

GENERATOR

VCC

50Ω

Figure 3. Test Circuit for Driver Propagation Delay, Transition Time, and Maximum Operating Frequency

DIN

VDIFF

tPLHD

tPHLD

VDIFF = DOUT+ –DOUT–

VOH

VOL

VOD

3V

1.5V

0V (DIFFERENTIAL)

0V

80%

20%

0V

DOUT+

DOUT–

tTLH

tTHL

Figure 4. Driver Propagation Delay and Transition Time Waveforms

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