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ADN4661BRZ-REEL7 Datasheet(PDF) 10 Page - Analog Devices |
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ADN4661BRZ-REEL7 Datasheet(HTML) 10 Page - Analog Devices |
10 / 12 page ADN4661 Rev. 0 | Page 10 of 12 THEORY OF OPERATION The ADN4661 is a single line driver for low voltage differential signaling. It takes a single-ended 3 V logic signal and converts it to a differential current output. The data can then be trans- mitted for considerable distances, over media such as a twisted- pair cable or PCB backplane, to an LVDS receiver, where it develops a voltage across a terminating resistor, RT. This resistor is chosen to match the characteristic impedance of the medium, typically around 100 Ω. The differential voltage is detected by the receiver and converted back into a single-ended logic signal. When DIN is high (Logic 1), current flows out of the DOUT+ pin (current source) through RT and back to the DOUT− pin (current sink). At the receiver, this current develops a positive differential voltage across RT (with respect to the inverting input) and results in a Logic 1 at the receiver output. When DIN is low (Logic 0), DOUT+ sinks current and DOUT− sources current. A negative differen- tial voltage across RT results in a Logic 0 at the receiver output. The output drive current is between ±2.5 mA and ±4.5 mA (typically ±3.55 mA), developing between ±250 mV and ±450 mV across a 100 Ω termination resistor. The received voltage is centered around the receiver offset of 1.2 V. Therefore, the noninverting receiver input for Logic 1 is typically (1.2 V + [355 mV/2]) = 1.377 V, and the inverting receiver input is (1.2 V − [355 mV/2]) = 1.023 V. For Logic 0, the inverting and noninverting output voltages are reversed. Note that because the differential voltage reverses polarity, the peak-to-peak voltage swing across RT is twice the differential voltage. Current-mode drivers offer considerable advantages over voltage mode drivers such as RS-422 drivers. The operating current remains fairly constant with increased switching frequency, whereas the current of voltage mode drivers increases exponentially in most cases. This is caused by the overlap as internal gates switch between high and low, which causes currents to flow from the device power supply to ground. A current-mode device simply reverses a constant current between its two outputs, with no significant overlap currents. This is similar to emitter-coupled logic (ECL) and positive emitter-coupled logic (PECL), but without the high quiescent current of ECL and PECL. APPLICATIONS INFORMATION Figure 21 shows a typical application for point-to-point data transmission using the ADN4661 as the driver and the LVDS receiver. ADN4661 LVDS RECEIVER 0.1µF VCC +3.3V 10µF TANTALUM + 0.1µF VCC +3.3V DOUT DIN DOUT+ DOUT– DIN+ DIN– 10µF TANTALUM + RT 100Ω GND GND Figure 21. Typical Application Circuit |
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