AD8303

REV. 0

–5–

Table I. Control-Logic Truth Table

CS

CLK RS

MSB

SHDN LDA/B

Serial Shift Register Function

DAC Register Function

H

X

H

X

H

H

No Effect

Latched

L

L

H

X

H

H

No Effect

Latched

L

H

H

X

H

H

No Effect

Latched

L

↑+

H

X

H

H

Shift-Register-Data Advanced One Bit Latched

↑+

L

H

X

H

H

No Effect

Latched

HX

H

X

H

↓–

No Effect

Updated with Current Shift Register Contents

H

X

H

X

H

L

No Effect

Transparent

X

X

L

H

H

X

No Effect

XX

↑+

H

H

H

No Effect

X

X

L

L

H

X

No Effect

Loaded with All Zeros

XX

↑+

X

H

H

No Effect

Latched All Zeros

X

X

X

X

L

X

No Effect

No Effect

NOTES

1

↑+ positive logic transition; ↓– negative logic transition; X Don’t Care.

PIN DESCRIPTIONS

Pin No.

Name

Function

1

AGND

Analog Ground.

DAC voltage output, 2.0475 V full scale with 0.5 mV per bit. An internal temperature stabilized reference

maintains a fixed full-scale voltage independent of time, temperature and power supply variations.

Reference Voltage Output Terminal. Very high output resistance must be buffered if used as a virtual

ground.

4

DGND

Digital Ground

5

CS

Chip Select, Active Low Input. Disables shift register loading when high. Does not effect LDA or LDB

operation.

6

CLK

Clock Input, positive edge clocks data into shift register.

7

SDI

Serial Data Input, input data loads directly into the shift register.

8

LDA

Load DAC register strobes, active low. Transfers shift register data to DAC A register. Asynchronous active

low input. See Control Logic Truth Table for operation.

9

RS

Resets DAC register to zero condition or half-scale depending on MSB pin. Asynchronous active low input.

10

LDB

Load DAC register strobes, active low. Transfers shift register data to DAC B register. Asynchronous active

low input. See Control Logic Truth Table for operation.

11

MSB

12

SHDN

13

Positive power supply input. Specified range of operation +2.7 V to +5.5 V

14

DAC voltage output, 2.0475 V full scale with 0.5 mV per bit. An internal temperature stabilized reference

maintains a fixed full-scale voltage independent of time, temperature and power supply variations.

PIN CONFIGURATION

14-Pin P-DIP (N-14)

14-Lead SOIC (R-14)

14

13

12

11

10

9

8

1

2

3

4

7

6

5

TOP VIEW

(Not to Scale)

AGND

MSB

SHDN

DGND

AD8303

LDA

RS

LDB

CS

CLK

SDI