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TC7107ACLP Datasheet(PDF) 9 Page - Microchip Technology |
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TC7107ACLP Datasheet(HTML) 9 Page - Microchip Technology |
9 / 34 page © 2008 Microchip Technology Inc. DS21455D-page 9 TC7106/A/TC7107/A 4.0 ANALOG SECTION In addition to the basic signal integrate and de- integrate cycles discussed, the circuit incorporates an auto-zero cycle. This cycle removes buffer amplifier, integrator, and comparator offset voltage error terms from the conversion. A true digital zero reading results without adjusting external potentiometers. A complete conversion consists of three cycles: an auto-zero, signal integrate, and reference integrate cycle. 4.1 Auto-Zero Cycle During the auto-zero cycle, the differential input signal is disconnected from the circuit by opening internal analog gates. The internal nodes are shorted to analog common (ground) to establish a zero input condition. Additional analog gates close a feedback loop around the integrator and comparator. This loop permits comparator offset voltage error compensation. The voltage level established on CAZ compensates for device offset voltages. The offset error referred to the input is less than 10 µV. The auto-zero cycle length is 1000 to 3000 counts. 4.2 Signal Integrate Cycle The auto-zero loop is entered and the internal differential inputs connect to VIN+ and VIN-. The differential input signal is integrated for a fixed time period. The TC7106/TC7106A signal integration period is 1000 clock periods or counts. The externally set clock frequency is divided by four before clocking the internal counters. The integration time period is: EQUATION 4-1: The differential input voltage must be within the device Common mode range when the converter and measured system share the same power supply common (ground). If the converter and measured system do not share the same power supply common, VIN- should be tied to analog common. Polarity is determined at the end of signal integrate phase. The sign bit is a true polarity indication, in that signals less than 1 LSB are correctly determined. This allows precision null detection limited only by device noise and auto-zero residual offsets. 4.3 Reference Integrate Phase The third phase is reference integrate or de-integrate. VIN- is internally connected to analog common and VIN+ is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output to return to zero. The time required for the output to return to zero is proportional to the input signal and is between 0 and 2000 counts. The digital reading displayed is: EQUATION 4-2: Where: FOSC = Externally set clock frequency T SI 4 F OSC ------------- 1000 × = 1000 V IN V REF ------------- = |
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