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202407B • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice. • March 20, 2013

AAT2612

DATA SHEET

Step-Down DC/DC Converter With Three High PSRR LDOs

ic capacitors. However, the design will allow for opera-

tion over a wide range of capacitor types.

The regulator comes with complete short circuit and ther-

mal protection. The combination of these two internal

protection circuits gives a comprehensive safety system

to guard against extreme adverse operating conditions.

Application Information

Step-down Converter

Input Capacitor

Select a 4.7uF to 10uF X7R or X5R ceramic capacitor for

the input. To estimate the required input capacitor value

and size, determine the acceptable input ripple voltage

the output voltage.

· 1 -

V

O

V

IN

C

V

O

V

IN

- ESR

·

f

S

V

PP

I

O

D =

V

O

V

IN

C

1

- ESR

·

S

V

PP

I

O

series resistor of output capacitor, and D is the duty

cycle.

The maximum input capacitor RMS current is:

I

· 1 -

V

O

V

IN

V

O

V

IN

The input capacitor RMS ripple current varies with the

input and output voltage and will always be less than or

equal to half of the total DC load current.

I

O

RMS

I

2

=

The maximum input voltage ripple also appears at 50%

duty cycle.

The input capacitor provides a low impedance loop for

the edges of pulsed current drawn by the AAT2612. Low

ESR/ESL X7R and X5R ceramic capacitors are ideal for

this function. To minimize parasitic inductances, the

capacitor should be placed as closely as possible to the

IC. This keeps the high frequency content of the input

current localized, minimizing EMI and input voltage rip-

ple.

The proper placement of the input capacitors (C1, C2,

and C3) is shown in the evaluation board layout in Figure

2.

A laboratory test set-up typically consists of two long

wires running from the bench power supply to the eval-

uation board input voltage pins. The inductance of these

wires, along with the low-ESR ceramic input capacitor,

can create a high Q network that may affect converter

performance. This problem often becomes apparent in

the form of excessive ringing in the output voltage dur-

ing load transients. Errors can also result in the loop

phase and gain measurements. Since the inductance of

a short PCB trace feeding the input voltage is signifi-

cantly lower than the power leads from the bench power

supply, most applications do not exhibit this problem.

In applications where the input power source lead induc-

tance cannot be reduced to a level that does not affect

the converter performance, a high ESR tantalum or alu-

minum electrolytic capacitor should be placed in parallel

with the low ESR/ESL bypass ceramic capacitor. This

dampens the high Q network and stabilizes the system.

Output Capacitor

The output capacitor limits the output ripple and pro-

vides holdup during large load transitions. A typical

4.7μF X5R or X7R ceramic capacitor typically provides

sufficient bulk capacitance to stabilize the output during

large load transitions and has the ESR and ESL charac-

teristics necessary for low output ripple.

The output voltage droop due to a load transient is dom-

inated by the capacitance of the ceramic output capacitor.

During a step increase in load current, the ceramic output

capacitor alone supplies the load current until the loop

responds. Within two or three switching cycles, the loop

responds and the inductor current increases to match the

load current demand. The relationship of the output volt-

age droop during the three switching cycles to the output

capacitance can be estimated by:

C

ΔI

LOAD

V