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AD744AR Datasheet(PDF) 10 Page - Analog Devices |
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AD744AR Datasheet(HTML) 10 Page - Analog Devices |
10 / 12 page REV. C AD744 –10– 19.95k 20k 9.96k 5k 8k 20V SPAN 10V SPAN DAC OUT POWER GND –VEE REF GND BIPOLAR OFFSET ADJUST 5k LSB MSB 10V VCC REF OUT REF IN 0.1 F 0.1 F 100 AD744 1 F +15V 1 F CLEAD 10pF –15V 100 GAIN ADJUST AD565A Figure 34. ±10 V Voltage Output Bipolar DAC Using the AD744 as an Output Buffer HIGH-SPEED OP AMP APPLICATIONS AND TECHNIQUES DAC Buffers (I-to-V Converters) Digital-to-analog converters which use bipolar transistors to switch currents into (or out of) their outputs can achieve very fast settling times. The AD565A, for example, is specified to settle to 12 bits in less than 250 ns, with a current output. How- ever, in many applications, a voltage output is desirable, and it would be useful – perhaps essential – that this I-to-V conversion be accomplished without increasing the settling time or without degrading the accuracy of the DAC. Figure 34 is a schematic of an AD565A DAC using an AD744 output buffer. The 10 pF CLEAD capacitor compensates for the DAC’s output capacitance, plus the 5.5 pF amplifier input capacitance. Figure 35 is an oscilloscope photo of the AD744’s output volt- age with a +10 V to 0 V step applied; this corresponds to an all “1s” to all “0s” code change on the DAC. Since the DAC is Figure 35. Upper Trace: AD744 Output Voltage for a +10 V to 0 V Step, Scale: 5 mV/div. Lower Trace: Logic Input Signal, Scale: 5 V/div. connected in the 20 V span mode, 1 LSB is equal to 4.88 mV. Output settling time for the AD565/AD744 combination is less than 500 ns to within a 2.44 mV, 1/2 LSB error band. A HIGH-SPEED, 3 OP AMP INSTRUMENTATION AMPLIFIER CIRCUIT The instrumentation amplifier circuit shown in Figure 36 can provide a range of gains from unity up to 1000 and higher. The circuit bandwidth is 4 MHz at a gain of 1 and 750 kHz at a gain of 10; settling time for the entire circuit is less than 2 µs to within 0.01% for a 10 V step, (G = 10). While the AD744 is not stable with 100% negative feedback (as when connected as a standard voltage follower), phase margin and therefore stability at unity gain may be increased to an accept- able level by placing the parallel combination of a resistor and a small lead capacitor between each amplifier’s output and its inverting input terminal. The only penalty associated with this method is a small band- width reduction at low gains. The optimum value for CLEAD may be determined from the graph of Figure 41. This technique can be used in the circuit of Figure 36 to achieve stable opera- tion at gains from unity to over 1000. AD744 +VS 1 F 1 F +15V COMM –15V –VS 1 F 1 F 0.1 F 0.1 F PIN 7 PIN 4 EACH AMPLIFIER A1 –IN 10k 7.5pF **10k AD744 A3 7.5pF **10k **10k 5pF **10k *1.5pF – 20pF (TRIM FOR BEST SETTLING TIME) SENSE 10k AD744 A2 +IN REFERENCE *VOLTRONICS SP20 TRIMMER CAPACITOR OR EQUIVALENT **RATIO MATCHED 1% METAL FILM RESISTORS 20,000 RG CIRCUIT GAIN = + 1 FOR OPTIONAL OFFSET ADJUSTMENT: TRIM A1, A3 USING TRIM PROCEDURE SHOWN IN FIGURE 21. RG Figure 36. A High Performance, 3 Op Amp Instrumentation Amplifier Circuit |
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