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AD668SQ Datasheet(PDF) 8 Page - Analog Devices |
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AD668SQ Datasheet(HTML) 8 Page - Analog Devices |
8 / 16 page AD668 REV. A –8– RL – a 200 Ω resistor with one end internally wired to the out- put pin. If a 200 Ω ±20% DAC output impedance is desired, R L should be shorted to IOUT. Grounding RL will provide a DAC output impedance of 100 Ω ±1%. As noted above, in voltage output configurations, a large portion of the DAC output cur- rent will flow through this pin. ACOM - as indicated in Figure 4, the current flowing out of this pin is effectively the complement of IOUT, varying with both analog and digital inputs. Using this current as a signal output is not generally advised, since it is untrimmed and its positive out- put compliance is limited to the logic low voltage. LCOM - the current in this node has been carefully configured to be independent of digital code when the output is into a vir- tual ground, thereby minimizing any detrimental effects of lad- der ground resistance on linearity. However, the current in this node is proportional to the analog input voltage and the ground drop here is responsible for the dc analog feedthrough. The nominal value of this current is approximately equal to the DAC full scale. IBPO - the bipolar offset current flows into this node, with volt- age compliance to VEE + 3V. This is a high impedance current source, and should be grounded if the offset current is not used. VEE - this voltage may be set anywhere from –10.8 V to –16.5 V. The current in this node consists of 1.2 times the bipo- lar offset current plus 500 µA of bias current for the reference amplifier’s front end. The negative supply current is indepen- dent of digital input but is linearly dependent on analog input. THCOM - is the ground point for the bandgap diode that gen- erates the threshold voltage. The current coming out of this node is the same as that flowing into VTH plus a code dependent number of base currents (see Figure 6). It is possible to intro- duce an offset between THCOM and the system common, thereby offsetting the effective logic threshold and positive out- put compliance voltage. VTH - as indicated earlier, if given sufficient positive bias cur- rent, this voltage will be 1.4 V above THCOM. The necessary bias current can readily be provided by a suitable resistor to any positive supply. As Figure 6 suggests, this node is directly coupled to the DAC output through several base to collector capacitances and hence, should be carefully decoupled to the analog ground. DIGITAL INPUTS - when a bit is in the high state, the input current is the leakage current of a reverse biased diode. When the bit is driven low, it must sink a base current to ground, and this base current will be proportional to the analog input. Note that the input current for Bit 2 will be twice that for Bits 3-12, and Bit 1’s current will be 4 times Bit 3’s, but all the currents will be below the value specified. APPLYING THE AD668 The following are some typical circuit configurations for the AD668. As Table II indicates, these represent only a sample of the possible implementations. 5 V REFIN, 1 V UNIPOLAR, UNBUFFERED VOLTAGE OUTPUT Figure 7 shows a typical topology for generating an unbuffered voltage output. RL (Pin 19) is grounded, producing a 100 Ω DAC output resistance that generates a 1.024 V output when the DAC current is at its full scale of 10.24 mA. The presence of low impedance loads will effect the output voltage swing di- rectly: an external load of 300 Ω will yield a total output resis- tance of 75 Ω, and a full scale output of 0.768 V. An external 100 Ω will reduce the total output resistance to 50 Ω and the full-scale voltage swing will drop to 0.512 V. Since the bipolar offset current is not used in this configuration, Pin 16 is con- nected to the analog ground plane. The input divider has been connected to produce a 5 V full scale reference input by shorting REFIN1 to the analog ground plane and using REFIN2 as the reference input. With a 5 V nominal full scale, the 10% to 120% reference input range falls between 0.5 V and 6 V. The effective input resistance in this mode is 5 k Ω (±20%). The ratio of the input divider has been intentionally skewed by 50 Ω to provide an optional external fine trim for gain adjust. A trim range of ±1% is provided by the 100 Ω trimming potentiometer shown in Figure 7. If trimming is not desired, a 50 Ω resistor may be used in place of the poten- tiometer to produce the specified gain accuracy, or, if a +1% nominal gain error is tolerable, the resistor may be omitted altogether. Figure 7. 5 V REFIN/1 V Unbuffered Unipolar Output 1.25 V REFIN, 1 V BIPOLAR, UNBUFFERED VOLTAGE OUTPUT Figure 8 demonstrates another unbuffered voltage output topol- ogy, this time implementing a bipolar output and a 1.25 V refer- ence input. The bipolar output is accomplished simply by tying Pin 16 to the output (Pin 20). Note that in this mode, when the digital inputs are all zeros and the analog input is at 1.25 V, –512 mV will be produced at the DAC output. Bipolar zero (0 VOUT) will be produced when the MSB is ON with all other bits OFF (100 . . . 00), and the full-scale voltage minus 1 LSB (511.75 mV) will be generated when all bits are ON. The input range of 1.25 V is generated by grounding REFIN2 (through an optional gain trim potentiometer or gain adjust 50 Ω resistor) and using REFIN1 as the reference input. The input resistance in this mode is also 5k. |
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