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ISPLSI5384VE-100LB272 Datasheet(PDF) 3 Page - Lattice Semiconductor |
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ISPLSI5384VE-100LB272 Datasheet(HTML) 3 Page - Lattice Semiconductor |
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3 / 22 page  Specifications ispLSI 5384VE 3 ispLSI 5000VE Description (Continued) The 32 registered macrocells in the GLB are driven by the 32 outputs from the PTSA or the PTSA bypass. Each macrocell contains a programmable XOR gate, a pro- grammable register/latch and the necessary clocks and control logic to allow combinatorial or registered opera- tion. The macrocells each have two outputs, combinatorial and registered. This dual output capability from the macrocell allows efficient use of the hardware resources. One output can be a registered function for example, while the other output can be an unrelated combinatorial function. A direct register input from the I/O pad facili- tates efficient use of this feature to construct high-speed input registers. Macrocell registers can be clocked from one of several global or product term clocks available on the device. A global and product term clock enable is also available to each register, eliminating the need to gate the clock to the macrocell registers. Reset for the macrocell register is provided from the global signal, its polarity is user- selectable. The macrocell register can be programmed to operate as a D-type register or a D-type latch. The 32 outputs from the GLB can drive both the Global Routing Pool and the device I/O cells. The Global Routing Pool contains one input from each macrocell output and one input from each I/O pin. The input buffer threshold has programmable TTL/3.3V/ 2.5V compatible levels. The output driver can source 4mA and sink 8mA in 3.3V mode. The output drivers have a separate VCCIO reference input which is inde- pendent of the main VCC supply for the device. This feature allows individual output drivers to drive either 3.3V (from the device VCC) or 2.5V (from the VCCIO pin) output levels while the device logic and the output current drive are powered from device supply (VCC). The output drivers also provide individually programmable edge rates and open drain capability. A programmable pullup resistor is provided to tie off unused inputs. Additionally, a programmable bus-hold latch is available to hold tristate outputs in their last valid state until the bus is driven again by some device. The ispLSI 5000VE Family features 3.3V, non-volatile in- system programmability for both the logic and the interconnect structures, providing the means to develop truly reconfigurable systems. Programming is achieved through the industry standard IEEE 1149.1-compliant Boundary Scan interface. Boundary Scan test is also supported through the same interface. An enhanced, multiple cell security scheme is provided that prevents reading of the JEDEC programming file when secured. After the device has been secured using this mechanism, the only way to clear the security is to execute a bulk-erase instruction. ispLSI 5000VE Family Members The ispLSI 5000VE Family ranges from 128 macrocells to 512 macrocells and operates from a 3.3V power supply. All family members will be available with multiple package options. The ispLSI 5000VE Family device matrix showing the various bondout options is shown in the table below. The interconnect structure (GRP) is very similar to Lattice's existing ispLSI 1000, 2000 and 3000 families, but with an enhanced interconnect structure for optimal pin locking and logic routing. This eliminates the need for registered I/O cells or an Output Routing Pool. The ispLSI 5000VE encompasses the innovative fea- tures of the ispLSI 5000VA family with several enhancements. The macrocell is optimized and the T- type flip flop option is removed. To improve the efficiency of design fits, the Product Term Reset Logic is simplified and the polarity option as well as the Global Preset function are removed. The programmable output-delay feature (skew option) is also removed. As a result, the ispLSI 5000VE is not JEDEC compatible with the ispLSI 5000VA. ispLSI 5000VA and 5000VE pinouts may differ in the same package, however all programming and power/ground pins are located in the same locations. Table 1. ispLSI 5000VE Family Package Type ispLSI 5128VE Device GLBs Macrocells 128 TQFP 256 fpBGA 272 BGA 388 fpBGA 388 BGA 4 128 96 I/O — — — — 8256 96 I/O 144 I/O 144 I/O — — 12 384 — 192 I/O 192 I/O — — 16 512 — 100 TQFP — 72 I/O — —192 I/O 192 I/O 256 I/O 256 I/O ispLSI 5256VE ispLSI 5384VE ispLSI 5512VE |
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