iCE40 HX-Series Ultra-Low Power Family

Lattice Semiconductor Corporation

(1.32, 03-OCT-2012)

www.latticesemi.com/

10

Internal Configuration Oscillator Frequency

Table 12 shows the operating frequency for the iCE40’s internal configuration oscillator.

Symbol

Oscillator

Mode

Frequency (MHz)

Description

Min.

Max.

Default

7

10

Default oscillator frequency. Slow enough to safely operate

with any SPI serial PROM.

Low

Frequency

21

30

Supported by most SPI serial Flash PROMs

High

Frequency

35

50

Supported by some high-speed SPI serial Flash PROMs

Off

0

0

Oscillator turned off by default after configuration to save

power.

Configuration Timing

Table 13 shows the maximum time to configure an iCE40HX device, by oscillator mode. The calculations use the

slowest frequency for a given oscillator mode from Table 12 and the maximum configuration bitstream size from

Table 1, which includes full RAM4K block initialization. The configuration bitstream selects the desired oscillator

mode based on the performance of the configuration data source.

Symbol

Description

Device

Default

Low Freq.

High Freq.

Units

Time from when minimum

Power-on Reset (POR)

threshold is reached until

user application starts.

iCE40HX1K

53

25

11

ms

iCE40HX4K

230

110

50

ms

iCE40HX8K

230

110

50

ms

Table 14 provides timing for the CRESET_B and CDONE pins.

Symbol

From

To

Description

All Grades

Units

Min.

Max.

CREST_B

CREST_B

Minimum CRESET_B Low pulse width required to restart

configuration, from falling edge to rising edge

200

—

ns

CDONE

High

PIO pins

active

Number of configuration clock cycles after CDONE goes

High before the PIO pins are activated.

—

49

Clock

cycles

SPI Peripheral Mode (Clock = SPI_SCK, cycles measured

rising-edge to rising-edge)

Depends on

SPI_SCK frequency

Table 15 provides various timing specifications for the SPI peripheral mode interface.

Symbol

From

To

Description

All Grades

Units

Min.

Max.

CRESET_B

SPI_SCK

Minimum time from a rising edge on CRESET_B until

the first SPI write operation, first SPI_SCK. During this

time, the iCE40HX FPGA is clearing its internal

configuration memory

300

—

µs

SPI_SI

SPI_SCK

Setup time on SPI_SI before the rising SPI_SCK clock

edge

12

—

ns

SPI_SCK

SPI_SI

Hold time on SPI_SI after the rising SPI_SCK clock edge

12

—

ns

SPI_SCK

SPI_SCK

SPI_SCK clock High time

20

—

ns

SPI_SCK

SPI_SCK

SPI_SCK clock Low time

20

—

ns

SPI_SCK

SPI_SCK

SPI_SCK clock period*

40

1,000

ns

SPI_SCK

SPI_SCK

Sustained SPI_SCK clock frequency*

1

25

MHz

* = Applies after sending the synchronization pattern.