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AX125 Datasheet(PDF) 11 Page - Microsemi Corporation |
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AX125 Datasheet(HTML) 11 Page - Microsemi Corporation |
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11 / 262 page  Axcelerator Family FPGAs Re vi s i on 18 1-5 Routing The AX hierarchical routing structure ties the logic modules, the embedded memory blocks, and the I/O modules together (Figure 1-8 on page 1-6). At the lowest level, in and between SuperClusters, there are three local routing structures: FastConnect, DirectConnect, and CarryConnect routing. DirectConnects provide the highest performance routing inside the SuperClusters by connecting a C-cell to the adjacent R-cell. DirectConnects do not require an antifuse to make the connection and achieve a signal propagation time of less than 0.1 ns. FastConnects provide high-performance, horizontal routing inside the SuperCluster and vertical routing to the SuperCluster immediately below it. Only one programmable connection is used in a FastConnect path, delivering a maximum routing delay of 0.4 ns. CarryConnects are used for routing carry logic between adjacent SuperClusters. They connect the FCO output of one two-bit, C-cell carry logic to the FCI input of the two-bit, C-cell carry logic of the SuperCluster below it. CarryConnects do not require an antifuse to make the connection and achieve a signal propagation time of less than 0.1 ns. The next level contains the core tile routing. Over the SuperClusters within a core tile, both vertical and horizontal tracks run across rows or columns, respectively. At the chip level, vertical and horizontal tracks extend across the full length of the device, both north-to-south and east-to-west. These tracks are composed of highway routing that extend the entire length of the device (segmented at core tile boundaries) as well as segmented routing of varying lengths. Figure 1-7 • I/O Cluster Arrangement I/O Cluster I/O Module CoreTile 4k RAM/ FIFO 4k RAM/ FIFO 4k RAM/ FIFO 4k RAM/ FIFO OutReg EnReg InReg I/O Module I/O Module RX RX RX RX TX TX B N I O B A K |
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