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APA300 Datasheet(PDF) 8 Page - Microsemi Corporation |
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APA300 Datasheet(HTML) 8 Page - Microsemi Corporation |
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8 / 174 page  ProASICPLUS Flash Family FPGAs 1- 4 v5.2 Routing Resources The routing structure of ProASICPLUS devices is designed to provide high performance through a flexible four- level hierarchy of routing resources: ultra-fast local resources, efficient long-line resources, high-speed, very long-line resources, and high performance global networks. The ultra-fast local resources are dedicated lines that allow the output of each tile to connect directly to every input of the eight surrounding tiles (Figure 1-4). The efficient long-line resources provide routing for longer distances and higher fanout connections. These resources vary in length (spanning 1, 2, or 4 tiles), run both vertically and horizontally, and cover the entire ProASICPLUS device (Figure 1-5 on page 1-5). Each tile can drive signals onto the efficient long-line resources, which can in turn access every input of every tile. Active buffers are inserted automatically by routing software to limit the loading effects due to distance and fanout. The high-speed, very long-line resources, which span the entire device with minimal delay, are used to route very long or very high fanout nets. (Figure 1-6 on page 1-6). The high-performance global networks are low-skew, high fanout nets that are accessible from external pins or from internal logic (Figure 1-7 on page 1-7). These nets are typically used to distribute clocks, resets, and other high fanout nets requiring a minimum skew. The global networks are implemented as clock trees, and signals can be introduced at any junction. These can be employed hierarchically with signals accessing every input on all tiles. Figure 1-4 • Ultra-Fast Local Resources L L L L L L Inputs Ultra-Fast Local Lines (connects a tile to the adjacent tile, I/O buffer, or memory block) L LL |
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