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A14100 Datasheet(PDF) 9 Page - Microsemi Corporation |
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A14100 Datasheet(HTML) 9 Page - Microsemi Corporation |
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9 / 90 page  R e visio n 3 2 -1 2 – Detailed Specifications This section of the datasheet is meant to familiarize the user with the architecture of the ACT 3 family of FPGA devices. A generic description of the family will be presented first, followed by a detailed description of the logic blocks, the routing structure, the antifuses, and the special function circuits. The on-chip circuitry required to program the devices is not covered. Topology The ACT 3 family architecture is composed of six key elements: Logic modules, I/O modules, I/O Pad Drivers, Routing Tracks, Clock Networks, and Programming and Test Circuits. The basic structure is similar for all devices in the family, differing only in the number of rows, columns, and I/Os. The array itself consists of alternating rows of modules and channels. The logic modules and channels are in the center of the array; the I/O modules are located along the array periphery. A simplified floor plan is depicted in Figure 2-1. Figure 2-1 • Generalized Floor Plan of ACT 3 Device IO IO IO IO IO IO C SC S S IO IO C C SC S S IO IO C C SC S S IO IO C BIO IO IO IO IO IO IO IO BIN S C C S S IO IO BIN S C C S S IO IO BIN S C C S S IO IO IO CLKM IO IO IO IO IO IO IO BIN S C IO CS SC SC S S IO IO C An Array with n rows and m columns Top I/Os Bottom I/Os Left I/Os Right I/Os Rows n+1 n n–1 • • • 2 1 0 Channels n+1 n n–1 • • • 2 1 0 n+2 0 1 2 3 4 5 c–1 c c+1 m m+1 m+2 m+3 Columns |
Similar Part No. - A14100 |
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Similar Description - A14100 |
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