AAT1121

1.5MHz, 250mA Step-Down Converter

DATA SHEET

11

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201974B • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice. • March 15, 2013

Output Voltage (V)

L1 (μH)

1.0

1.5

1.2

2.2

1.5

2.7

1.8

3.0

2.5

3.9

3.0

4.7

3.3

5.6

Table 1: Inductor Values.

The 3.0μH CDRH2D09 series inductor selected from

Sumida has a 150m DCR and a 470mA DC current rat-

ing. At full load, the inductor DC loss is 9.375mW which

gives a 2.08% loss in efficiency for a 250mA, 1.8V out-

put.

Input Capacitor

Select a 4.7μF to 10μF X7R or X5R ceramic capacitor for

the input. To estimate the required input capacitor size,

⎛⎞

· 1 -

⎝⎠

⎛⎞

- ESR

·

⎝⎠

⎛⎞

· 1 -

=

⎝⎠

1

4

1

⎛⎞

- ESR

·

⎝⎠

Always examine the ceramic capacitor DC voltage coef-

ficient characteristics when selecting the proper value.

For example, the capacitance of a 10μF, 6.3V, X5R ceram-

ic capacitor with 5.0V DC applied is actually about 6μF.

The maximum input capacitor RMS current is:

⎛⎞

· 1 -

⎝⎠

The input capacitor RMS ripple current varies with the

input and output voltage and will always be less than or

equal to half of the total DC load current.

⎛⎞

· 1 -

⎝⎠

1

2

RMS(MAX)

I

2

=

The term

⎛⎞

· 1 -

⎝⎠

appears in both the input voltage

ripple and input capacitor RMS current equations and is

voltage ripple and the input capacitor RMS current ripple

are a maximum at 50% duty cycle.

The input capacitor provides a low impedance loop for

the edges of pulsed current drawn by the AAT1121. Low

ESR/ESL X7R and X5R ceramic capacitors are ideal for

this function. To minimize stray inductance, the capacitor

should be placed as closely as possible to the IC. This

keeps the high frequency content of the input current

localized, minimizing EMI and input voltage ripple.

The proper placement of the input capacitor (C1) can be

seen in the evaluation board layout in Figure 2.

A laboratory test set-up typically consists of two long

wires running from the bench power supply to the evalu-

ation board input voltage pins. The inductance of these

wires, along with the low-ESR ceramic input capacitor,

can create a high Q network that may affect converter

performance. This problem often becomes apparent in

the form of excessive ringing in the output voltage dur-

ing load transients. Errors in the loop phase and gain

measurements can also result.

Since the inductance of a short PCB trace feeding the

input voltage is significantly lower than the power leads

from the bench power supply, most applications do not

exhibit this problem.

In applications where the input power source lead induc-

tance cannot be reduced to a level that does not affect

the converter performance, a high ESR tantalum or alu-

minum electrolytic should be placed in parallel with the

low ESR, ESL bypass ceramic. This dampens the high Q

network and stabilizes the system.