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MP6900DJ Datasheet(PDF) 6 Page - Monolithic Power Systems |
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MP6900DJ Datasheet(HTML) 6 Page - Monolithic Power Systems |
6 / 12 page MP6900- FAST TURN-OFF INTELLIGENT CONTROLLER MP6900 Rev. 1.12 www.MonolithicPower.com 6 9/19/2012 MPS Proprietary Information. Patent Protected. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. BLOCK DIAGRAM Figure 1—Functional Block Diagram OPERATION The MP6900 supports operation in CCM, DCM and Quasi-Resonant topologies. Operating in either a DCM or Quasi-Resonant topology, the control circuitry controls the gate in forward mode and will turn the gate off when the MOSFET current is fairly low. In CCM operation, the control circuitry turns off the gate when very fast transients occur. Blanking The control circuitry contains a blanking function. When it pulls the MOSFET on/off, it makes sure that the on/off state at least lasts for some time. The turn on blanking time is ~1.6us, which determines the minimum on-time. During the turn on blanking period, the turn off threshold is not totally blanked, but changes the threshold voltage to ~+50mV (instead of -30mV). This assures that the part can always be turned off even during the turn on blanking period. (Albeit slower, so it is not recommended to set the synchronous period less than 1.6us at CCM condition in flyback converter, otherwise shoot through may occur) VD Clamp Because VD can go as high as 180V, a High- Voltage JFET is used at the input. To avoid excessive currents when Vg goes below -0.7V, a small resistor is recommended between VD and the drain of the external MOSFET. Under-Voltage Lockout (UVLO) When the VDD is below UVLO threshold, the part is in sleep mode and the Vg pin is pulled low by a 10k Ω resistor. Enable pin The Enable function is only available on the SOIC-8 package. If EN is pulled low, the part is in sleep mode. |
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