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PCA9544ABS Datasheet(PDF) 10 Page - NXP Semiconductors |
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PCA9544ABS Datasheet(HTML) 10 Page - NXP Semiconductors |
10 / 26 page PCA9544A_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 15 June 2009 10 of 26 NXP Semiconductors PCA9544A 4-channel I2C-bus multiplexer with interrupt logic 7.4 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also, a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Fig 10. System configuration 002aaa966 MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER SDA SCL I2C-BUS MULTIPLEXER SLAVE Fig 11. Acknowledgement on the I2C-bus 002aaa987 S START condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver SCL from master |
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