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74LVC821A Datasheet(PDF) 5 Page - NXP Semiconductors |
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74LVC821A Datasheet(HTML) 5 Page - NXP Semiconductors |
5 / 20 page 74LVC821A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 4 — 23 November 2012 5 of 20 NXP Semiconductors 74LVC821A 10-bit D-type flip-flop; 5 V tolerance; positive-edge trigger; 3-state 5. Pinning information 5.1 Pinning 5.2 Pin description (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 5. Pin configuration SO24 and (T)SSOP24 Fig 6. Pin configuration DHVQFN24 821A OE VCC D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 D8 Q8 D9 Q9 GND CP 001aaa676 1 2 3 4 5 6 7 8 9 10 11 12 14 13 16 15 18 17 20 19 22 21 24 23 001aaa680 821A Transparent top view Q9 D8 D9 Q8 D7 Q7 D6 Q6 D5 Q5 D4 Q4 D3 Q3 D2 Q2 D1 Q1 D0 Q0 11 14 10 15 9 16 8 17 7 18 6 19 5 20 4 21 3 22 2 23 terminal 1 index area GND(1) Table 2. Pin description Symbol Pin Description OE 1 output enable input (active LOW) CP 13 clock input (LOW-to-HIGH, edge-triggered) D[0:9] 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 data input Q[0:9] 23, 22, 21, 20, 19, 18, 17, 16, 15, 14 3-state flip-flop output GND 12 ground (0 V) VCC 24 supply voltage |
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