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LY6125616ML-10T Datasheet(PDF) 9 Page - Lyontek Inc. |
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LY6125616ML-10T Datasheet(HTML) 9 Page - Lyontek Inc. |
9 / 14 page LY6125616 Rev. 2.4 5V 256K X 16 BIT HIGH SPEED CMOS SRAM Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 8 ® WRITE CYCLE 3 (LB#,UB# Controlled) (1,2,5,6) Dout Din Data Valid tDW tDH (4) High-Z tWHZ WE# LB#,UB# tCW CE# Address tWR tAS tAW tWC tWP tBW Notes : 1.WE#,CE#, LB#, UB# must be high during all address transitions. 2.A write occurs during the overlap of a low CE#, low WE#, LB# or UB# = low. 3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE#, LB#, UB# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. DATA RETENTION CHARACTERISTICS PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT VCC for Data Retention VDR CE# V ≧ CC - 0.2V 2.0 - 5.5 V Data Retention Current IDR VCC = 2.0V CE# V ≧ CC - 0.2V other pins at 0.2V or VCC-0.2V 10 - - 10 mA 15/20/25 - 0.05 2 mA 15/20/25LL - 10 50 µA Chip Disable to Data Retention Time tCDR See Data Retention Waveforms (below) 0 - - ns Recovery Time tR tRC* - - ns tRC* = Read Cycle Time DATA RETENTION WAVEFORM Vcc CE# VDR ≧ 2.0V CE# V ≧ cc-0.2V Vcc(min.) VIH tR tCDR VIH Vcc(min.) |
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