LY62W5128WL-70LL datasheet(6/17 Pages) LYONTEK

Part #	LY62W5128WL-70LL

Description	512K X 8 BIT LOW POWER CMOS SRAM

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Manufacturer	LYONTEK [Lyontek Inc.]

Direct Link	http://www.lyontek.com.tw

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LY62W5128

Rev. 1.11

512K X 8 BIT LOW POWER CMOS SRAM

Lyontek Inc. reserves the rights to change the specifications and products without notice.

5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.

TEL: 886-3-6668838

FAX: 886-3-6668836

5

®

Notes:

1. VIH(max) = VCC + 3.0V for pulse width less than 10ns.

2. VIL(min) = VSS - 3.0V for pulse width less than 10ns.

3. Over/Undershoot specifications are characterized, not 100% tested.

4. Typical values are included for reference only and are not guaranteed or tested.

Typical values are measured at VCC = VCC(TYP.) and TA = 25℃

5. This parameter is measured at VCC = 3.0V

CAPACITANCE (TA = 25 , f

℃

= 1.0MHz)

PARAMETER

SYMBOL

MIN.

MAX

UNIT

Input Capacitance

CIN

-

6

pF

Input/Output Capacitance

CI/O

-

8

pF

Note : These parameters are guaranteed by device characterization, but not production tested.

AC TEST CONDITIONS

Input Pulse Levels

0.2V to VCC -0.2V

Input Rise and Fall Times

3ns

Input and Output Timing Reference Levels

1.5V

Output Load

CL = 30pF + 1TTL, IOH/IOL = -2mA/4mA

AC ELECTRICAL CHARACTERISTICS

(1) READ CYCLE

PARAMETER

SYM.

LY62W5128-55

LY62W5128-70

UNIT

MIN.

MAX.

MIN.

MAX.

Read Cycle Time

tRC

55

-

70

-

ns

Address Access Time

tAA

-

55

-

70

ns

Chip Enable Access Time

tACE

-

55

-

70

ns

Output Enable Access Time

tOE

-

30

-

35

ns

Chip Enable to Output in Low-Z

tCLZ*

10

-

10

-

ns

Output Enable to Output in Low-Z

tOLZ*5

-

5

-

ns

Chip Disable to Output in High-Z

tCHZ*

-

20

-

25

ns

Output Disable to Output in High-Z

tOHZ*

-

20

-

25

ns

Output Hold from Address Change

tOH

10

-

10

-

ns

(2) WRITE CYCLE

PARAMETER

SYM.

LY62W5128-55

LY62W5128-70

UNIT

MIN.

MAX.

MIN.

MAX.

Write Cycle Time

tWC

55

-

70

-

ns

Address Valid to End of Write

tAW

50

-

60

-

ns

Chip Enable to End of Write

tCW

50

-

60

-

ns

Address Set-up Time

tAS

0-0

-

ns

Write Pulse Width

tWP

45

-

55

-

ns

Write Recovery Time

tWR

0-0

-

ns

Data to Write Time Overlap

tDW

25

-

30

-

ns

Data Hold from End of Write Time

tDH

0-0

-

ns

Output Active from End of Write

tOW*5

-

5

-

ns

Write to Output in High-Z

tWHZ*

-

20

-

25

ns

*These parameters are guaranteed by device characterization, but not production tested.

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