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AK4616 Datasheet(PDF) 10 Page - Asahi Kasei Microsystems |
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AK4616 Datasheet(HTML) 10 Page - Asahi Kasei Microsystems |
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10 / 46 page  [AK4616] MS1437-J-01 2012/11 - 10 - スイッチング特性 (Ta=-40 ∼+85°C; A3V31, A3V32= D3V3=3.0∼ 3.6V; D1V8=1.7∼ 1.9V; CL=20pF; unless otherwise specified) Parameter Symbol min typ max Unit Master Clock Timing External Clock 256fs: Pulse Width Low Pulse Width High 384fs: Pulse Width Low Pulse Width High 512fs: Pulse Width Low Pulse Width High fCLK tCLKL tCLKH fCLK tCLKL tCLKH fCLK tCLKL tCLKH 2.048 32 32 3.072 22 22 4.096 16 16 12.288 18.432 24.576 MHz ns ns MHz ns ns MHz ns ns LRCK Timing (Slave mode) Stereo mode (TDM bit = “0”) LRCK frequency Duty Cycle fs Duty 8 45 48 55 kHz % TDM256 mode (TDM bit = “1”) LRCK frequency “H” time “L” time fs tLRH tLRL 8 1/256fs 1/256fs 48 kHz ns ns Audio Interface Timing (Slave mode) Stereo mode (TDM bit = “0”) BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK “ ↑” (Note 12) BICK “ ↑” to LRCK Edge (Note 12) LRCK to SDTO(MSB) (Except I2S mode) BICK “ ↓” to SDTO SDTI Hold Time SDTI Setup Time tBCK tBCKL tBCKH tLRB tBLR tLRS tBSD tSDH tSDS 324 130 130 20 20 50 50 80 80 ns ns ns ns ns ns ns ns ns TDM256 mode (TDM bit = “1”) BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK “ ↑” (Note 12) BICK “ ↑” to LRCK Edge (Note 12) SDTO Setup time BICK “ ↑” SDTO Hold time BICK “ ↑” SDTI Hold Time SDTI Setup Time tBCK tBCKL tBCKH tLRB tBLR tBSS tBSH tSDH tSDS 81 33 33 23 23 6 5 10 10 ns ns ns ns ns ns ns ns ns Note 12. この規格値はLRCKのエッジとBICKの “↑” が重ならないように規定しています。 |
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