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LY61L102416AGL-10T Datasheet(PDF) 5 Page - Lyontek Inc. |
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LY61L102416AGL-10T Datasheet(HTML) 5 Page - Lyontek Inc. |
5 / 13 page LY61L102416A Rev. 1.4 1024K X 16 BIT HIGH SPEED CMOS SRAM Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, lndustry E . Rd. 9, Science-Based Industrial Park, Hsinchu 300, Taiwan TEL: 886-3-6668838 FAX: 886-3-6668836 4 ® Standby Power Supply Current ISB1 CE# V ≧ CC - 0.2V; Other pin is at 0.2V or Vcc-0.2V - 4 40 mA Notes: 1. VIH(max) = VCC + 2.0V for pulse width less than 6ns. 2. VIL(min) = VSS - 2.0V for pulse width less than 6ns. 3. Over/Undershoot specifications are characterized on engineering evaluation stage, not for mass production test. 4. Typical values are included for reference only and are not guaranteed or tested. Typical valued are measured at VCC = VCC(TYP.) and TA = 25℃ CAPACITANCE (TA = 25 , f ℃ = 1.0MHz) PARAMETER SYMBOL MIN. MAX UNIT Input Capacitance CIN - 8 pF Input/Output Capacitance CI/O - 10 pF Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS speed 10/12ns Input Pulse Levels 0.2V to Vcc-0.2V Input Rise and Fall Times 3ns Input and Output Timing Reference Levels Vcc/2 Output Load CL = 30pF + 1TTL, IOH/IOL = -8mA/4mA AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE PARAMETER SYM. LY61L102416A-10 LY61L102416A-12 UNIT MIN. MAX. MIN. MAX. Read Cycle Time tRC 10 - 12 - ns Address Access Time tAA - 10 - 12 ns Chip Enable Access Time tACE -10 - 12 ns Output Enable Access Time tOE -4.5 - 5 ns Chip Enable to Output in Low-Z tCLZ*2 - 3 - ns Output Enable to Output in Low-Z tOLZ* 0 - 0 - ns Chip Disable to Output in High-Z tCHZ* - 4 - 5 ns Output Disable to Output in High-Z tOHZ*- 4 - 5 ns Output Hold from Address Change tOH 2- 2 - ns LB#, UB# Access Time tBA -4.5 - 5 ns LB#, UB# to High-Z Output tBHZ* - 4 - 5 ns LB#, UB# to Low-Z Output tBLZ* 0 - 0 - ns (2) WRITE CYCLE PARAMETER SYM. LY61L102416A-10 LY61L102416A-12 UNIT MIN. MAX. MIN. MAX. Write Cycle Time tWC 10 - 12 - ns Address Valid to End of Write tAW 8 - 10 - ns Chip Enable to End of Write tCW 8 - 10 - ns Address Set-up Time tAS 0-0- ns Write Pulse Width tWP 8 - 10 - ns |
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