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74AUP2G86GS Datasheet(PDF) 3 Page - NXP Semiconductors |
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74AUP2G86GS Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 21 page 74AUP2G86 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 7 — 14 June 2012 3 of 21 NXP Semiconductors 74AUP2G86 Low-power dual 2-input EXCLUSIVE-OR gate 6. Pinning information 6.1 Pinning Fig 3. Logic diagram (one gate) mna040 Y B A Fig 4. Pin configuration SOT765-1 Fig 5. Pin configuration SOT833-1, SOT1089, SOT1116 and SOT1203 74AUP2G86 1A VCC 1B 1Y 2Y 2B GND 2A 001aaf173 1 2 3 4 6 5 8 7 74AUP2G86 2B 1Y VCC 2A 2Y 1B 1A GND 001aaf174 36 27 18 45 Transparent top view Fig 6. Pin configuration SOT996-2 Fig 7. Pin configuration SOT902-2 001aaj918 74AUP2G86 Transparent top view 8 7 6 5 1 2 3 4 1A 1B 2Y GND VCC 1Y 2B 2A 001aaf175 1B 2B 1A 2Y 1Y 2A Transparent top view 3 6 1 5 7 2 terminal 1 index area 74AUP2G86 |
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