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MP2493 Datasheet(PDF) 7 Page - Monolithic Power Systems |
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MP2493 Datasheet(HTML) 7 Page - Monolithic Power Systems |
7 / 12 page MP2493 – 2A, 36V, LOW EMI STEP-DOWN WITH PROGRAMMABLE OUTPUT CURRENT LIMIT MP2493 Rev. 0.9 www.MonolithicPower.com 7 4/23/2010 MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. OPERATION Main Control Loop The MP2493 is a current mode buck regulator. That is, the error amplifier (EA) output voltage is proportional to the peak inductor current. At the beginning of a cycle, the integrated high side power switch M1 (Fig.1) is off; the EA output voltage is higher than the current sense amplifier output; and the current comparator’s output is low. The rising edge of the 130kHz clock signal sets the RS Flip-Flop. Its output turns on M1 thus connecting the SW pin and inductor to the input supply. The increasing inductor current is sensed and amplified by the Current Sense Amplifier. Ramp compensation is added to Current Sense Amplifier output and compared to the Error Amplifier output by the PWM Comparator. When the Current Sense Amplifier plus Slope Compensation signal exceeds the EA output voltage, the RS Flip-Flop is reset and the MP2493 reverts to its initial M1 off state. If the Current Sense Amplifier plus Slope Compensation signal does not exceed the COMP voltage, then the falling edge of the CLK resets the Flip-Flop. The output of the Error Amplifier integrates the voltage difference between the feedback and the 0.8V bandgap reference. The polarity is such that a FB pin voltage lower than 0.8V increases the EA output voltage. Since the EA output voltage is proportional to the peak inductor current, an increase in its voltage increases current delivered to the output. An external Schottky Diode (D1) carries the inductor current when M1 is off. Load Current Limiting Loop The output current information is sensed via the ISP and ISN pins. The regulation threshold is set at 100mV. If VSENSE, the difference of VISP and VISN, is less than 100mV, the output voltage of the power supply will be set by the FB pin. If VSENSE reaches 100mV, the current limit loop will pull down SS and regulate the output at a constant current determined by the external sense resistor. The external capacitor on SS pin is the dominant compensation capacitor for load current regulation loop. The capacitor has normal value of 100nF, which will put the bandwidth of load current regulation loop to be less than 1 kHz. When VSENSE is higher than 100mV, SS will not drop down to the final regulation level immediately. It will cause the load current to be higher than the programmed level for a short period. A fast comparator is added to shut down power switch when the average load current is higher than 120% of the programmed current limit level. An inductor DC resistance (DCR) or accurate sense resistor can be used for load current sensing. |
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