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34LC02 Datasheet(PDF) 10 Page - Microchip Technology |
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34LC02 Datasheet(HTML) 10 Page - Microchip Technology |
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10 / 32 page  34AA02/34LC02 DS22029D-page 10 © 2008 Microchip Technology Inc. 6.0 READ OPERATION Read operations are initiated in the same way as write operations, with the exception that the R/W bit of the slave address is set to ‘1’. There are three basic types of read operations: current address read, random read and sequential read. 6.1 Current Address Read The 34XX02 contains an address counter that maintains the address of the last word accessed, inter- nally incremented by ‘1’. Therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n+1. Upon receipt of the slave address with R/W bit set to ‘1’, the 34XX02 issues an acknowledge and transmits the 8-bit data word. The master will not acknowledge the transfer, but does generate a Stop condition and the 34XX02 discontinues transmission (Figure 6-1). 6.2 Random Read Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, the word address must first be set. This is done by sending the word address to the 34XX02 as part of a write operation. Once the word address is sent, the master generates a Start condition following the acknowledge. This terminates the write operation, but not before the internal Address Pointer is set. The master then issues the control byte again, but with the R/W bit set to a ‘1’. The 34XX02 then issues an acknowledge and transmits the 8-bit data word. The master will not acknowledge the transfer, but does generate a Stop condition and the 34XX02 discontinues transmission (Figure 6-2). 6.3 Sequential Read Sequential reads are initiated in the same way as a random read, with the exception that after the 34XX02 transmits the first data byte, the master issues acknowl- edge, as opposed to a Stop condition in a random read. This directs the 34XX02 to transmit the next sequen- tially addressed 8-bit word (Figure 6-3). To provide sequential reads, the 34XX02 contains an internal Address Pointer, which is incremented by one at the completion of each operation. This Address Pointer allows the entire memory contents to be serially read during one operation. 6.4 Contiguous Addressing Across Multiple Devices The Chip Select bits (A2, A1, A0) can be used to expand the contiguous address space for up to 16K bits by adding up to eight 34XX02 devices on the same bus. In this case, software can use A0 of the control byte as address bit A8; A1 as address bit A9, and A2 as address bit A10. It is not possible to sequentially read across device boundaries. 6.5 Noise Protection and Brown-Out The 34XX02 employs a VCC threshold detector circuit which disables the internal erase/write logic if the VCC is below 1.35V at nominal conditions. The SCL and SDA inputs have Schmitt Trigger and filter circuits which suppress noise spikes to assure proper device operation, even on a noisy bus. FIGURE 6-1: CURRENT ADDRESS READ SP Bus Activity Master SDA Line Bus Activity S T O P Control Byte Data (n) A C K N O A C K S T A R T |
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Similar Description - 34LC02 |
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