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DS50PCI402SQ Datasheet(PDF) 1 Page - Texas Instruments

Part # DS50PCI402SQ
Description  DS50PCI402 2.5 Gbps / 5.0 Gbps 4 Lane PCI Express Repeater with Equalization and De-Emphasis
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

DS50PCI402SQ Datasheet(HTML) 1 Page - Texas Instruments

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DS50PCI402
www.ti.com
SNLS320H – APRIL 2010 – REVISED MARCH 2013
DS50PCI402 2.5 Gbps / 5.0 Gbps 4 Lane PCI Express Repeater with
Equalization and De-Emphasis
Check for Samples: DS50PCI402
1
FEATURES
DESCRIPTION
The DS50PCI402 is a low power, 4 lane bidirectional
2
Input and Output signal conditioning
buffer/equalizer designed specifically for PCI Express
increases PCIe reach in backplanes and
Gen1 and Gen2 applications. The device performs
cables
both receive equalization and transmit de-emphasis,
0.09 UI of residual deterministic jitter at 5Gbps
allowing maximum flexibility of physical placement
after 42” of FR4 (with Input EQ)
within a system. The receiver is capable of opening
an input eye that is completely closed due to inter-
0.11 UI of residual deterministic jitter at 5Gbps
symbol interference (ISI) induced by the interconnect
after 7m of PCIe Cable (with Input EQ)
medium.
0.09 UI of residual deterministic jitter at 5Gbps
The transmitter de-emphasis level can be set by the
with 28” of FR4 (with Output DE)
user
depending
on
the
distance
from
the
0.13 UI of residual deterministic jitter at 5Gbps
DS50PCI402 to the PCI Express endpoint. The
with 7m of PCIe Cable (with Output DE)
DS50PCI402 contains PCI Express specific functions
Adjustable Transmit VOD 800 to 1200mVp-p
such as Transmit Idle, RX Detection, and Beacon
signal pass through.
Automatic and manual Receiver Detection and
input termination control circuitry
The device provides automatic receive detection
Automatic power management on an
circuitry
which
controls
the
input
termination
impedance. By automatically reflecting the current
individual lane basis via SMBus
load impedance seen on the outputs back to the
Adjustable electrical idle detect threshold.
corresponding inputs the DS50PCI402 becomes
Data rate optimized 3-stage equalization to 27
completely transparent to both the PCIe root complex
dB gain
and endpoint. An internal rate detection circuit is
included to detect if an incoming data stream is at
Data rate optimized 6-level 0 to 12 dB transmit
Gen2 data rates, and adjusts the de-emphasis on it's
de-emphasis
output accordingly. The signal conditioning provided
Flow-thru pinout in 10mmx5.5mm 54-pin
by the device allows systems to upgrade from Gen1
leadless WQFN package
data rates to Gen2 without reducing their physical
Single supply operation at 2.5V
reach. This is true for FR4 applications such as
backplanes, as well as cable interconnect.
>6kV HBM ESD rating
-10 to 85°C operating temperature range
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2010–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


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