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TPS73218-Q1 Datasheet(PDF) 2 Page - Texas Instruments |
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TPS73218-Q1 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 21 page TPS73218-Q1 SBVS229A – JUNE 2013 – REVISED AUGUST 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS Over operating junction temperature range unless otherwise noted. (1) PARAMETER TPS732xx-Q1 UNIT VIN range –0.3 to 6 V VEN range –0.3 to 6 V VOUT range –0.3 to 5.5 V VNR range –0.3 to 6 V Peak output current Internally limited Output short-circuit duration Indefinite Continuous total power dissipation See Thermal Information Table Ambient operating temperature range, TA –40 to 125 °C Junction temperature range, TJ –55 to 150 °C Storage temperature range –65 to 150 °C ESD rating, HBM 2 kV ESD rating, CDM 750 V (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. THERMAL INFORMATION TPS732xx-Q1(3) THERMAL METRIC(1)(2) DRB DCQ DBV UNIT 8 PINS 6 PINS 5 PINS θJA Junction-to-ambient thermal resistance 47.8 70.4 180 θJCtop Junction-to-case (top) thermal resistance 83 70 64 θJB Junction-to-board thermal resistance N/A N/A 35 °C/W ψJT Junction-to-top characterization parameter 2.1 6.8 N/A ψJB Junction-to-board characterization parameter 17.8 30.1 N/A θJCbot Junction-to-case (bottom) thermal resistance 12.1 6.3 N/A (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A. (2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator. (3) Thermal data for the DRB, DCQ, and DRV packages are derived by thermal simulations based on JEDEC-standard methodology as specified in the JESD51 series. The following assumptions are used in the simulations: (a) Ni. DRB: The exposed pad is connected to the PCB ground layer through a 2x2 thermal via array. ii. DCQ: The exposed pad is connected to the PCB ground layer through a 3x2 thermal via array. iii. DBV: There is no exposed pad with the DBV package. (b) Ni. DRB: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper coverage. ii. DCQ: Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage. iii. DBV: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper coverage. (c) This data was generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3 in × 3 in copper area. To understand the effects of the copper area on thermal performance, see the Power Dissipation section of this data sheet. 2 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS73218-Q1 |
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