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A5841SLW Datasheet(PDF) 2 Page - Allegro MicroSystems

Part # A5841SLW
Description  BiMOS II 8-BIT SERIAL-INPUT, LATCHED DRIVERS
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Manufacturer  ALLEGRO [Allegro MicroSystems]
Direct Link  http://www.allegromicro.com
Logo ALLEGRO - Allegro MicroSystems

A5841SLW Datasheet(HTML) 2 Page - Allegro MicroSystems

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5841 AND 5842
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1985, 2000 Allegro MicroSystems, Inc.
FUNCTIONAL BLOCK DIAGRAM
(‘A’ Package Shown)
MOS
BIPOLAR
OUT 1 OUT 2
LOGIC
GROUND
STROBE
OUTPUT ENABLE
(ACTIVE LOW)
SERIAL
DATA OUT
6
8
7
Dwg. FP-013-2
9
POWER
GROUND
SUB
OUT 3
CLOCK
SERIAL
DATA IN
SERIAL-PARALLEL SHIFT REGISTER
LATCHES
VDD
LOGIC
SUPPLY
2
3
4
18
OUT 6 OUT 7 OUT 8
17
16
13
12
11
OUT 4 OUT 5
15
14
5
K
10
1
50
75
100
125
150
2.5
0.5
0
AMBIENT TEMPERATURE IN
°C
2.0
1.5
1.0
25
Dwg. GP-022-4
18-LEAD SOIC, RθJA = 80
°C/W
20-LEAD SOIC, RθJA = 70
°C/W
18-PIN DIP, RθJA = 60
°C/W
SERIAL
DATA OUT
POWER
GROUND
SERIAL
DATA IN
OUTPUT
ENABLE
OUT1
OUT2
OUT 3
NO
CONNECT.
NO
CONNECT.
NC
NC
LOGIC SUPPLY
STROBE
GROUND
CLOCK
OUT 6
OUT7
OUT 8
OUT5
OUT4
Dwg. PP-029-3
13
14
15
16
17
19
12
18
20
11
1
2
3
8
9
4
5
6
7
10
SUB
CLK
SUB
V
DD
ST
OE
POWER
GROUND
K
A5841SLW
& A5842SLW


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