UCN5818AF datasheet(3/8 Pages) ALLEGRO

Part #	UCN5818AF

Description	BiMOS II 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS

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Manufacturer	ALLEGRO [Allegro MicroSystems]

Direct Link	http://www.allegromicro.com

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5818-F

32-BIT SERIAL-INPUT,

LATCHED SOURCE DRIVERS

WITH ACTIVE-DMOS PULL-DOWNS

www.allegromicro.com

ELECTRICAL CHARACTERISTICS at TA = + 25°C, VBB = 60 V unless otherwise noted.

Limits @ VDD = 5 V Limits @ VDD = 12 V

Characteristic

Symbol

Test Conditions

Mln.

Typ.

Max.

Min.

Typ.

Max.

Units

Output Leakage Current

ICEX

VOUT = 0 V, TA = +70°C

—

-5.0

-15

—

-5.0

-15

µA

Output Voltage

VOUT(1)

IOUT = -25 mA

58

58.5

—

58

58.5

—

V

VOUT(0)

IOUT = 1 mA

—

2.0

3.0

———

V

IOUT = 2 mA

———

—

2.0

3.5

V

Output Pull-Down Current

IOUT(0)

VOUT = 5 V to VBB

2.0

3.5

—

———

mA

VOUT = 20 V to VBB

———

8.0

13

—

mA

Input Voltage

VIN(1)

3.5

—

5.3

10.5

—

12.3

V

VIN(0)

-0.3

—

+0.8

-0.3

—

+0.8

V

Input Current

IIN(1)

VIN = VDD

—

0.05

0.5

—

0.1

1.0

µA

IIN(0)

VIN = 0.8 V

—

-0.05

-0.5

—

-0.1

-1.0

µA

Serial Data Output Voltage

VOUT(1)

IOUT = -200 µA

4.5

4.7

—

11.7

11.8

—

V

VOUT(0)

IOUT = 200 µA

—

200

250

—

100

200

mV

Maximum Clock Frequency

fclk

3.3*

——

———

MHz

Supply Current

IDD(1)

All Outputs High

—

100

300

—

200

500

µA

IDD(0)

All Outputs Low

—

100

300

—

200

500

µA

IBB(1)

Outputs High, No Load

—

3.0

6.0

—

3.0

6.0

mA

IBB(0)

Outputs Low

—

10

100

—

10

100

µA

Blanking to Output Delay

tPHL

CL = 30 pF, 50% to 50%

—

2000

——

1000

—

ns

tPLH

CL = 30 pF, 50% to 50%

—

1000

——

850

—

ns

Output Fall Time

tf

CL = 30 pF, 90% to 10%

—

1450

——

650

—

ns

Output Rise Time

tr

CL = 30 pF, 10% to 90%

—

650

——

700

—

ns

Negative current is defined as coming out of (sourcing) the specified device terminal.

* Operation at a clock frequency greater than the specified minimum value is possible but not warranteed.

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