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5821AND Datasheet(PDF) 2 Page - Allegro MicroSystems |
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5821AND Datasheet(HTML) 2 Page - Allegro MicroSystems |
2 / 8 page 5821 AND 5822 8-BIT SERIAL-INPUT, LATCHED DRIVERS 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 MOS BIPOLAR OUT 1 OUT 2 LOGIC GROUND STROBE OUTPUT ENABLE (ACTIVE LOW) SERIAL DATA OUT 5 7 6 Dwg. FP-013A OUT 3 CLOCK SERIAL DATA IN SERIAL-PARALLEL SHIFT REGISTER LATCHES VDD LOGIC SUPPLY 1 2 3 16 OUT 6 OUT 7 OUT 8 15 14 11 10 9 OUT 4 OUT 5 13 12 8 4 POWER GROUND SUB FUNCTIONAL BLOCK DIAGRAM TYPICAL INPUT CIRCUITS Dwg. No. A-14,314 Dwg. EP-010-3 IN V DD Dwg. EP-010-4A IN V DD STROBE & OUTPUT ENABLE CLOCK & SERIAL DATA IN Copyright © 1985, 2000, Allegro MicroSystems, Inc. Number of Outputs ON UCN5821A Max. Allowable Duty Cycle (IOUT = 200 mA at Ambient Temperature of VDD = 12 V) 25 °C40°C50°C60°C70°C 8 90% 79% 72% 65% 57% 7 100% 90% 82% 74% 65% 6 100% 100% 96% 86% 76% 5 100% 100% 100% 100% 91% 4 100% 100% 100% 100% 100% 3 100% 100% 100% 100% 100% 2 100% 100% 100% 100% 100% 1 100% 100% 100% 100% 100% Number of Outputs ON UCN5821LW Max. Allowable Duty Cycle (IOUT = 200 mA at Ambient Temperature of VDD = 12 V) 25 °C40°C50°C60°C70°C 8 67% 59% 54% 49% 43% 7 77% 68% 62% 56% 49% 6 90% 79% 72% 65% 57% 5 100% 95% 86% 78% 68% 4 100% 100% 100% 98% 86% 3 100% 100% 100% 100% 100% 2 100% 100% 100% 100% 100% 1 100% 100% 100% 100% 100% TYPICAL OUTPUT DRIVER OUT SUB 7.2K 3K NOTE — There is an indeterminate resistance between logic ground and power ground. For proper operation, these terminals must be externally connected together. |
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