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SMV512K32HFGMPR Datasheet(PDF) 7 Page - Texas Instruments |
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SMV512K32HFGMPR Datasheet(HTML) 7 Page - Texas Instruments |
7 / 25 page SMV512K32-SP www.ti.com SLVSA21H – JUNE 2011 – REVISED JULY 2013 Table 3. Example Control Settings for Resetting MBE SEQUENCE E1Z E2 GZ WZ MBE I/O MODE MODE 1 L H L H L DQ[31:0] Data out Normal read mode with EDAC enabled MBE driven high when single bit or multiple bit error 2 L H L H H DQ[31:0] Data out (depending on user configuration) is detected during read 3 H L L H H DQ[31:0] Data out Memory disabled 4 H L H H H → L DQ[31:0] Tri-state Outputs tri-stated and MBE pulled low by load R 5 L H H H L DQ[31:0] Tri-state Read at a last known error free address(1) 6 L H L H L DQ[31:0] Data out Output enable-controlled read(2) (1) During this operation MBE drive circuitry in the memory is tri-stated but MBE is held low by the 1-k Ω resistor to ground. (2) During this operation MBE is actively driven low by the MBE drive circuitry in the memory after a time, tGLMV, and the memory is back to the original state corresponding to normal read mode with EDAC enabled. Read Operations A combination of E1Z low, E2 high and WZ high defines a read cycle. GZ low enables the outputs to drive read data to the DQ pins. Read access time is measured from the latter of device enable, output enable or valid address to valid data output. • SRAM read cycle 1 (Figure 4): Address controlled access is initiated by a change in address inputs while device is selected with WZ high and GZ low. Valid data appears on DQ[31:0] after a specified tAVQV is satisfied. Outputs remain active throughout the entire cycle. As long as the device enable and output enable are active, the minimum time between valid address changes is specified by the read cycle time tAVAV. • SRAM read cycle 2 (Figure 5): Chip-enable controlled access is initiated by the latter of either E1Z or E2 going active while GZ is low, WZ is high, and address remains stable for the entire cycle. After the specified time tETQV, the 32-bit word addressed by A[18:0] is accessed and appears at DQ[31:0]. • SRAM read cycle 3 (Figure 6): Output-enable controlled access is initiated by GZ going active while E1Z and E2 are asserted, WZ is de-asserted, and address is stable. Read access time is tGLQV unless tAVQV or tETQV have not been satisfied. If EDAC is turned on during read operation: • If MBE is low, data is valid. • If MBE is high, data is corrupted (dependent on EDAC programming configuration on A[12], MBE can indicate a single bit or double bit error). Single bit error is correctable by EDAC. Table 4. AC Characteristics Read Cycle (1) SYMBOL PARAMETER MIN MAX UNIT FIGURE tAVAV1 Read cycle time 20 ns Figure 4 tAVQV1 Address to data valid from address change(2) 20 ns Figure 4 tAXQX Output hold time 7.5 ns Figure 4 tGLQX1 GZ-controlled output enable time 3.5 ns Figure 6 tGLQV GZ-controlled output data valid 8.6 ns Figure 6 tGHQZ1 GZ-controlled output enable tri-state time 3.5 5 ns Figure 6 tETQX E-controlled output enable time 3.5 ns Figure 5 tETQV E-controlled access time 20 ns Figure 5 tEFQZ E-controlled tri-state time 3.5 5 ns Figure 5 tAVMV Address to error flag valid 20 ns Figure 4 tAXMX Address to error flag hold time from address change 7.5 ns Figure 4 (1) TC = -55°C to 125°C, VDD1 = 1.7 V to 1.9 V, VDD2 = 3 V to 3.6 V (unless otherwise noted). (2) 20 ns at 5-pF load. Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: SMV512K32-SP |
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