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LXT973 PHY Transceiver

Specification Update

249737, Revision 10.0

20 March 2007

5.0 Errata

Item 4:

MDIO Interface and Repeated Polling

Problem

Repeated polling of odd-numbered registers via the MDIO interface randomly returns the

contents of the previous even register.

Implication

Managed applications may not obtain the correct register contents when a particular

register is monitored for device status.

Workaround None.

Status

This erratum has been previously fixed.

Item 5:

3.3 V Fiber Speed Selection

Problem

In fiber mode, the hardware configuration pins (SD_2P5V/SPEEDn) set the speed rather

than set the signal detect voltage threshold.

Implication

Setting the SD_2P5V/SPEEDn to Low sets the device in 10 Mbps operation, which is not

supported in fiber mode. The signal detect function defaults to 2.5 V PECL thresholds.

The signal detect input is unreliable when driven from a 3.3 V PECL source.

Workaround To select 100 Mbps operation in fiber mode, tie the SD_2P5V/SPEEDn configuration pins

High through a 10 K

Ω resistor to VCC.

To properly terminate the signal detect input, tie the SDn pins High through a 10 K

Ω

resistor.

There is no workaround to enable the SD function when using a 3.3 V optical module.

Status

This erratum has been previously fixed.

Item 6:

Far-End Fault Reporting

Problem

If a link partner continuously sends successive Far-End Fault (FEF) codes (three sets of

84 1s followed by a 0), the LXT973 PHY Transceiver sets the Remote Fault bit High

(Register bit 1.4 = 1) and drops link (Register bit 1.2 = 0). Register bit 1.4 is cleared after a

Read and is not set High again while the Far-End Fault signal is present.

Implication

If the MAC reads Register bit 1.4 more than once under a continuous Far-End Fault

condition, a Far-End Fault is not indicated after the first read.

Once a remote fault has been indicated by Register bit 1.4 = 1, the following sequence

can be used to monitor the remote-fault status.

Managed Systems:

• Write Register 0 = 0x6100: Forces the port to 100 Mbps full-duplex internal loopback,

link is up, Register bit 1.2 = 1 and Register bit 1.4 = 0.

• Wait: Approximately 100 mS.

• Write Register 0 = 0x2100: Forces the port into 100 Mbps full-duplex. If Far-End Fault

is present, Register bit 1.4 = 1 indicates Far-End Fault and Register bit 1.2 = 0

indicates link is down.

Status

This erratum has been previously fixed.