TPS7H1101-SP

TPS7H1201-HT

SLVSAS4F – JUNE 2013 – REVISED DECEMBER 2013

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THERMAL INFORMATION

(1) (2) (3)

TPS7H1x01

HKS

HKR

HKR

(HeatSlug_up_no

(HeatSlug_down

(HeatSlug_down_no

UNITS

Underfill)

16 PINS

16 PINS

16 PINS

75.4

30.7

86.6

0.4

N/A

N/A

4.8

69

59.3

Junction-to-top characterization

1.1

2.4

5

°C/W

Junction-to-board characterization

53.5

12.3

63.2

Junction-to-case (bottom) thermal

N/A

0.6

0.6

(1)

Do not allow package body temperature to exceed 265°C at any time or permanent damage may result.

(2)

Maximum power dissipation may be limited by overcurrent protection.

(3)

Test board conditions:

(a) 2.5 inches × 2.5 inches, 4 layers, thickness: 0.062 inch

(b) 2 oz. copper traces located on the top of the PCB

(c) 2 oz. copper ground planes on the 2 internal layers and bottom layer

(d) 48 0.010 inch thermal vias located under the device package

(4)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(5)

where distortion starts to substantially increase. Thermal management of the PCB should strive to keep the junction temperature at or

below 220°C for best performance and long-term reliability.

(6)

where distortion starts to substantially increase. Thermal management of the PCB should strive to keep the junction temperature at or

below 230°C for best performance and long-term reliability.

(7)

Values listed in the underfill column were derived using properties from a composite, generic silver filled epoxy underfill. They are not

product specific.

(8)

The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(9)

The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(10) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(11) The junction-to-top characterization parameter,

from the simulation data for obtaining

(12) The junction-to-board characterization parameter,

from the simulation data for obtaining

(13) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

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