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TAS5412-Q1 Datasheet(PDF) 7 Page - Texas Instruments |
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TAS5412-Q1 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 38 page  TAS5412-Q1 www.ti.com SLOS685A – AUGUST 2013 – REVISED OCTOBER 2013 ELECTRICAL CHARACTERISTICS Test conditions (unless otherwise noted): TCase= 25°C, PVDD = 14.4 V, RL= 4 Ω, fS = 417 kHz, Pout= 1 W/ch, Rext = 20 kΩ, AES17 filter, master-mode operation (see application diagram) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OPERATING CURRENT IPVDD_IDLE Both channels in MUTE mode 125 175 PVDD idle current mA IPVDD_Hi-Z Both channels in Hi-Z mode 60 IPVDD_STBY PVDD standby current STANDBY mode, T J = 85°C 2 12 µA OUTPUT POWER 4 Ω, PVDD = 14.4 V, THD+N = 1%, 1 kHz, T c= 75°C 23 4 Ω, PVDD = 14.4 V, THD+N = 10%, 1 kHz, T c= 75°C 25 28 4 Ω, PVDD = 24 V, THD+N = 1%, 1 kHz, T c= 75°C 62 4 Ω, PVDD = 24 V, THD+N = 10%, 1 kHz, T c= 75°C 63 79 2 Ω, PVDD = 14.4 V, THD+N = 1%, 1 kHz, T c= 75°C 38 POUT Output power per channel W 2 Ω, PVDD = 14.4 V, THD+N = 10%, 1 kHz, T c= 75°C 40 50 PBTL 2- Ω operation, PVDD = 24 V, THD+N = 10%, 150 1 kHz, T c= 75°C PBTL 1- Ω operation, PVDD = 14.4 V, THD+N = 10%, 90 1 kHz, T c= 75°C 2 channels operating, 23-W output power per ch, L = 10 % EFFP Power efficiency 90 µH, T J = 85°C AUDIO PERFORMANCE VNOISE Noise voltage at output G = 26 dB, zero input, and A-weighting 60 100 µV Crosstalk Channel crosstalk 1 W, G = 26 dB, 1 kHz 60 75 dB PSRR Power-supply rejection ratio G = 26 dB, PVDD = 14.4 Vdc + 1 Vrms, f = 1 kHz 60 75 dB THD+N Total harmonic distortion + noise P = 1 W, G = 26 dB, f = 1 kHz, 0°C = T J = 75°C 0.02% 0.1% 336 357 378 Switching frequency selectable for AM interference fS Switching frequency 392 417 442 kHz avoidance 470 500 530 RAIN Analog input resistance Internal shunt resistance on each input pin 63 82 106 k Ω AC-coupled common-mode input voltage (zero VIN_CM Common-mode input voltage 1.3 Vrms differential input) VCM_INT Internal common-mode input bias voltage Internal bias applied to IN_M pin 3.37 V 11 12 13 19 20 21 Source impedance = 0 Ω, gain measurement taken at 1 G Voltage gain (VO / VIN) dB W of power per channel 25 26 27 31 32 33 GCH Channel-to-channel variation Any gain commanded –1 0 1 dB PWM OUTPUT STAGE rDSon FET drain-to-source resistance Not including bond-wire resistance, T J= 25°C 75 95 m Ω Zero input signal, dc offset reduction enabled, and VO_OFFSET Output offset voltage ±10 ±50 mV G = 26 dB PVDD OVERVOLTAGE (OV) PROTECTION VOV PVDD overvoltage shutdown 24.6 26.4 28.2 V PVDD UNDERVOLTAGE (UV) PROTECTION VUV_SET PVDD undervoltage shutdown 5 5.3 5.6 V VUV_CLEAR Recovery voltage for PVDD UV 6.2 6.6 7.2 V AVDD VA_BYP A_BYP pin voltage 6.5 V VA_BYP_UV_SET A_BYP UV voltage 3.5 V VA_BYP_UV_CLEAR Recovery voltage A_BYP UV 4.3 V DVDD VD_BYP D_BYP pin voltage 3.3 V POWER-ON RESET (POR) Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: TAS5412-Q1 |
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