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SN65LVDS822RGZR Datasheet(PDF) 7 Page - Texas Instruments |
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SN65LVDS822RGZR Datasheet(HTML) 7 Page - Texas Instruments |
7 / 27 page SN65LVDS822 www.ti.com SLLSEE8A – SEPTEMBER 2013 – REVISED OCTOBER 2013 ABSOLUTE MAXIMUM RATINGS (1) VALUE UNIT Supply voltage range(2), VDD , VDDIO –0.3 to 4 V Voltage range at any input When VDDIO > 0 V –0.5 to 4 terminal V Voltage range at any When VDDIO ≤ 0 V –0.5 to (VDDIO + 0.7) output terminal Human Body Model(3) (all pins) ±3 Electrostatic discharge kV Charged-Device Mode(4) (all pins) ±1.5 Storage temperature, TSTG –65 to 150 °C Maximum junction temperature, TJ 125 °C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to the GND terminals (3) In accordance with JEDEC Standard 22, Test Method A114-B (4) In accordance with JEDEC Standard 22, Test Method C101 THERMAL INFORMATION SN65LVDS822 THERMAL METRIC(1) RGZ UNITS 48 PINS θJA Junction-to-ambient thermal resistance(2) 30.1 θJCtop Junction-to-case (top) thermal resistance(3) 18.1 θJB Junction-to-board thermal resistance(4) 6.9 °C/W ψJT Junction-to-top characterization parameter(5) 0.2 ψJB Junction-to-board characterization parameter(6) 6.9 θJCbot Junction-to-case (bottom) thermal resistance(7) 0.7 (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. (3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. (4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. (5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). (6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). (7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer xxx Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links :SN65LVDS822 |
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