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MSP430TCH5ERHBR Datasheet(PDF) 6 Page - Texas Instruments |
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MSP430TCH5ERHBR Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 67 page  MSP430TCH5E SLAS895 – DECEMBER 2013 www.ti.com Table 2. Terminal Functions TERMINAL NO. I/O DESCRIPTION NAME PW28 RHB32 P1.0/ General-purpose digital I/O pin TA0CLK/ Timer0_A, clock signal TACLK input ACLK/ 2 31 I/O ACLK signal output A0 ADC10 analog input A0 CA0 Comparator_A+, CA0 input P1.1/ General-purpose digital I/O pin TA0.0/ Timer0_A, capture: CCI0A input, compare: Out0 output / BSL transmit UCA0RXD/ USCI_A0 receive data input in UART mode, 3 1 I/O UCA0SOMI/ USCI_A0 slave data out/master in SPI mode A1/ ADC10 analog input A1 CA1 Comparator_A+, CA1 input P1.2/ General-purpose digital I/O pin TA0.1/ Timer0_A, capture: CCI1A input, compare: Out1 output UCA0TXD/ USCI_A0 transmit data output in UART mode, 4 2 I/O UCA0SIMO/ USCI_A0 slave data in/master out in SPI mode, A2/ ADC10 analog input A2 CA2 Comparator_A+, CA2 input P1.3/ General-purpose digital I/O pin ADC10CLK/ ADC10, conversion clock output A3/ ADC10 analog input A3 5 3 I/O VREF-/VEREF-/ ADC10 negative reference voltage CA3/ Comparator_A+, CA3 input CAOUT Comparator_A+, output P1.4/ General-purpose digital I/O pin SMCLK/ SMCLK signal output UCB0STE/ USCI_B0 slave transmit enable UCA0CLK/ USCI_A0 clock input/output 6 4 I/O A4/ ADC10 analog input A4 VREF+/VEREF+ ADC10 positive reference voltage / CA4/ Comparator_A+, CA4 input TCK JTAG test clock, input terminal for device programming and test P1.5/ General-purpose digital I/O pin TA0.0/ Timer0_A, compare: Out0 output / BSL receive UCB0CLK/ USCI_B0 clock input/output, UCA0STE/ 7 5 I/O USCI_A0 slave transmit enable A5/ ADC10 analog input A5 CA5/ Comparator_A+, CA5 input TMS JTAG test mode select, input terminal for device programming and test P1.6/ General-purpose digital I/O pin TA0.1/ Timer0_A, compare: Out1 output A6/ ADC10 analog input A6 CA6/ 22 21 I/O Comparator_A+, CA6 input UCB0SOMI/ USCI_B0 slave out/master in SPI mode, UCB0SCL/ USCI_B0 SCL I2C clock in I2C mode TDI/TCLK JTAG test data input or test clock input during programming and test 6 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: MSP430TCH5E |
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