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ONET1151LRGER Datasheet(PDF) 2 Page - Texas Instruments

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Part # ONET1151LRGER
Description  11.3 Gbps Low-Power Laser Diode Driver
Download  31 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ONET1151LRGER Datasheet(HTML) 2 Page - Texas Instruments

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background image
PD
ADR0
ADR1
DIS
SDA
SCK
2
1
3
4
5
6
17
18
16
15
14
13
8
7
9 10 11 12
23
24
22 21 20 19
BIAS
GND
VCC
COMP
MONB
MONP
ONET1101L
24 Lead QFN
³ RGE´
ONET1151L
24-Lead QFN
ONET1151L
SLLSEI7 – DECEMBER 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
24-Pin, RoHS-Compliant, QFN Package, 4 mm x 4 mm
With a Lead Pitch of 0,5 mm
(TOP VIEW)
Table 1. PIN DESCRIPTION
PIN
Type
Description
NAME
NO.
ADR0
2
Digital-in
I2C address programming pin. Leave this pad open for a default address of 0001000.
Pulling the pin to VCC changes the first address bit to 1 (address = 0001001).
ADR1
3
Digital-in
I2C address programming pin. Leave this pad open for a default address of 0001000.
Pulling the pin to VCC changes the second address bit to 1 (address = 0001010).
BIAS
18
Analog
Sinks or sources the bias current for the laser in both APC and open loop modes
COMP
15
Analog
Compensation pin used to control the bandwidth of the APC loop. Connect a 0.01-µF
capacitor to ground.
DIN+
9
Analog-in
Noninverted data input. On-chip differentially 100
Ω terminated to DIN–. Must be AC
coupled.
DIN–
10
Analog-in
Inverted data input. On-chip differentially 100
Ω terminated to DIN+. Must be AC coupled.
DIS
4
Digital-in
Disables both bias and modulation currents when set to high state. Includes a 10-k
Ω pullup
resistor to VCC. Toggle to reset a fault condition.
FLT
7
Digital-out
Fault detection flag. High level indicates that a fault has occurred. Open-drain output.
Requires an external 4.7-k
Ω to 10-kΩ pullup resistor to VCC for proper operation.
GND
8, 11, 17, EP
Supply
Circuit ground. Exposed die pad (EP) must be grounded.
MOD+
20, 21
CML-out
Noninverted modulation current output. IMOD flows into this pin when input data is high.
MOD–
22, 23
CML-out
Inverted modulation current output. IMOD flows into this pin when input data is low.
MONB
13
Analog-out
Bias current monitor. Sources a 1% replica of the bias current. Connect an external resistor
to ground (GND) to use the analog monitor (DMONB = 0). If the voltage at this pin exceeds
1.16 V, a fault is triggered. Typically choose a resistor to give MONB voltage of 0.8 V at the
maximum desired bias current. If the digital monitor function is used (DMONB = 1), the
resistor must be removed.
2
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Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: ONET1151L


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