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LMK00334RTVT Datasheet(PDF) 8 Page - Texas Instruments |
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LMK00334RTVT Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 25 page  LMK00334 SNAS635 – DECEMBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Unless otherwise specified: Vcc = 3.3 V ± 5%, Vcco = 3.3 V ± 5%, 2.5 V ± 5%, -40 °C ≤ TA ≤ 85 °C, CLKin driven differentially, input slew rate ≥ 3 V/ns. Typical values represent most likely parametric norms at Vcc = 3.3 V, Vcco = 3.3 V, TA = 25 °C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. (1) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT fCLKin0 = 100 MHz -84 fCLKin0 = 200 MHz -82 fOFFSET > 50 kHz, ISOMUX Mux Isolation, CLKin0 to CLKin1 dBc PCLKinX = 0 dBm fCLKin0 = 500 MHz -71 fCLKin0 = 1000 MHz -65 Crystal Interface (OSCin, OSCout) FCLK External Clock Frequency Range(6) OSCin driven single-ended, OSCout floating 250 MHz Fundamental mode crystal ESR ≤ 200 Ω (10 FXTAL Crystal Frequency Range 10 40 MHz to 30 MHz) ESR ≤ 125 Ω (30 to 40 MHz)(7) CIN OSCin Input Capacitance 1 pF HCSL Outputs (CLKoutAn/CLKoutAn*, CLKoutBn/CLKoutBn*) fCLKout Output Frequency Range(6) RL = 50 Ω to GND, CL ≤ 5 pF DC 400 MHz PCIe Gen 3, PLL BW Additive RMS Phase Jitter for PCIe CLKin: 100 MHz, JitterADD_PCle = 2–5 MHz, CDR = 10 0.03 0.15 ps 3.0(6) Slew rate ≥ 0.6 V/ns MHz CLKin: 100 MHz, 77 Slew rate ≥ 3 V/ns Additive RMS Jitter Integration Vcco = 3.3 V, RT = 50 JitterADD fs Bandwidth 1 MHz to 20 MHz(8) Ω to GND CLKin: 156.25 MHz, 86 Slew rate ≥ 2.7 V/ns CLKin: 100 MHz, -161.3 Slew rate ≥ 3 V/ns Vcco = 3.3 V, RT = 50 Noise Floor Noise Floor fOFFSET ≥ 10 MHz (9) (10) dBc/Hz Ω to GND CLKin: 156.25 MHz, -156.3 Slew rate ≥ 2.7 V/ns DUTY Duty Cycle(6) 50% input clock duty cycle 45 55 % 520 810 920 mV VOH Output High Voltage TA = 25 °C, DC Measurement, RT = 50 Ω to GND -150 0.5 150 mV VOL Output Low Voltage 250 350 460 mV VCROSS Absolute Crossing Voltage(6)(11) RL = 50 Ω to GND, CL ≤ 5 pF 140 mV ΔVCROSS Total Variation of VCROSS (6) (11) Output Rise Time 20% to 250 MHz, Uniform transmission line up to 10 tR 300 500 ps 80%(11)(12) in. with 50- Ω characteristic impedance, RL = 50 Ω to GND, CL ≤ 5 pF tF Output Fall Time 80% to 20%(11)(12) 300 500 ps (6) Specification is ensured by characterization and is not tested in production. (7) The ESR requirements stated must be met to ensure that the oscillator circuitry has no startup issues. However, lower ESR values for the crystal may be necessary to stay below the maximum power dissipation (drive level) specification of the crystal. Refer to Crystal Interface for crystal drive level considerations. (8) For the 100 MHz and 156.25 MHz clock input conditions, Additive RMS Jitter (JADD) is calculated using Method #1: JADD = SQRT(JOUT 2 - JSOURCE 2), where J OUT is the total RMS jitter measured at the output driver and JSOURCE is the RMS jitter of the clock source applied to CLKin. For the 625 MHz clock input condition, Additive RMS Jitter is approximated using Method #2: JADD = SQRT(2*10 dBc/10) / (2* π*fCLK), where dBc is the phase noise power of the Output Noise Floor integrated from 1 to 20 MHz bandwidth. The phase noise power can be calculated as: dBc = Noise Floor + 10*log10(20 MHz - 1 MHz). The additive RMS jitter was approximated for 625 MHz using Method #2 because the RMS jitter of the clock source was not sufficiently low enough to allow practical use of Method #1. Refer to the “Noise Floor vs. CLKin Slew Rate” and “RMS Jitter vs. CLKin Slew Rate” plots in TYPICAL CHARACTERISTICS. (9) The noise floor of the output buffer is measured as the far-out phase noise of the buffer. Typically this offset is ≥ 10 MHz, but for lower frequencies this measurement offset can be as low as 5 MHz due to measurement equipment limitations. (10) Phase noise floor will degrade as the clock input slew rate is reduced. Compared to a single-ended clock, a differential clock input (LVPECL, LVDS) will be less susceptible to degradation in noise floor at lower slew rates due to its common mode noise rejection. However, it is recommended to use the highest possible input slew rate for differential clocks to achieve optimal noise floor performance at the device outputs. (11) AC timing parameters for HCSL or CMOS are dependent on output capacitive loading. (12) Parameter is specified by design, not tested in production. 8 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMK00334 |
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