LMK00338

SNAS636 – DECEMBER 2013

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ELECTRICAL CHARACTERISTICS (continued)

Unless otherwise specified: Vcc = 3.3 V ± 5%, Vcco = 3.3 V ± 5%, 2.5 V ± 5%, -40 °C

differentially, input slew rate

= 25 °C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured.

(1)(2)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

-84

-82

Mux Isolation, CLKin0 to CLKin1

dBc

-71

-65

Crystal Interface (OSCin, OSCout)

OSCin driven single-ended, OSCout floating

250

MHz

Fundamental mode crystal ESR

≤ 200 Ω (10

Crystal Frequency Range

10

40

MHz

to 30 MHz) ESR

OSCin Input Capacitance

1

pF

HCSL Outputs (CLKoutAn/CLKoutAn*, CLKoutBn/CLKoutBn*)

DC

400

MHz

PCIe Gen 3, PLL BW

Additive RMS Phase Jitter for PCIe

CLKin: 100 MHz,

= 2–5 MHz, CDR = 10

0.03

0.15

ps

Slew rate

≥ 0.6 V/ns

MHz

CLKin: 100 MHz,

77

Slew rate

≥ 3 V/ns

Additive RMS Jitter Integration

Vcco = 3.3 V,

fs

RT = 50

Ω to GND

CLKin: 156.25 MHz,

86

Slew rate

≥ 2.7 V/ns

CLKin: 100 MHz,

-161.3

Slew rate

≥ 3 V/ns

Vcco = 3.3 V,

Noise Floor

(10) (11)

dBc/Hz

RT = 50

Ω to GND

CLKin: 156.25 MHz,

-156.3

Slew rate

≥ 2.7 V/ns

DUTY

50% input clock duty cycle

45

55

%

520

810

920

mV

Output High Voltage

GND

-150

0.5

150

mV

Output Low Voltage

160

350

460

mV

140

mV

Output Rise Time 20% to

250 MHz, Uniform transmission line up to 10

300

500

ps

in. with 50-

Ω characteristic impedance, RL =

50

300

500

ps

(8)

Specification is ensured by characterization and is not tested in production.

(9)

The ESR requirements stated must be met to ensure that the oscillator circuitry has no startup issues. However, lower ESR values for

the crystal may be necessary to stay below the maximum power dissipation (drive level) specification of the crystal. Refer to Crystal

Interface for crystal drive level considerations.

(10) The noise floor of the output buffer is measured as the far-out phase noise of the buffer. Typically this offset is

≥ 10 MHz, but for lower

frequencies this measurement offset can be as low as 5 MHz due to measurement equipment limitations.

(11) Phase noise floor will degrade as the clock input slew rate is reduced. Compared to a single-ended clock, a differential clock input

(LVPECL, LVDS) will be less susceptible to degradation in noise floor at lower slew rates due to its common mode noise rejection.

However, it is recommended to use the highest possible input slew rate for differential clocks to achieve optimal noise floor performance

at the device outputs.

(12) AC timing parameters for HCSL or CMOS are dependent on output capacitive loading.

(13) Parameter is specified by design, not tested in production.

8

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