ZSC31010

Data Sheet

May 25, 2011

© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.8

All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without

the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.

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List of Figures

Figure 2.1

RBicLite™ ZSC31010 Block Diagram ...................................................................................................14

Figure 2.2

DAC Output Timing for Highest Update Rate......................................................................................18

Figure 3.1

General Working Mode........................................................................................................................21

Figure 3.2

Manchester Duty Cycle........................................................................................................................22

Figure 3.3

19-Bit Write Frame...............................................................................................................................23

Figure 3.4

Read Acknowledge..............................................................................................................................23

Figure 3.5

Digital Output (NOM) Bridge Readings ...............................................................................................24

Figure 3.6

Digital Output (NOM) Bridge Readings with Temperature ..................................................................24

Figure 3.7

Read EEPROM Contents ....................................................................................................................25

Figure 3.8

Transmission of a Number of Data Packets ........................................................................................25

Figure 3.9

ZACwire™ Output Timing for Lower Update Rates.............................................................................26

Figure 4.1

Rail-to-Rail Ratiometric Voltage Output...............................................................................................38

Figure 4.2

Absolute Analog Voltage Output..........................................................................................................39

Figure 4.3

Ratiometric Output, Temperature Compensation via Internal Diode...................................................40

Figure 6.1

RBicLite™ Pin-Out Diagram ..................................................................................................................43

List of Tables

Table 1.1

Absolute Maximum Ratings ...................................................................................................................8

Table 1.2

Recommended Operating Conditions ...................................................................................................8

Table 1.3

Supply / Regulation Characteristics.......................................................................................................9

Table 1.4

Parameters for Analog Front-End (AFE) ...............................................................................................9

Table 1.5

EEPROM Parameters............................................................................................................................9

Table 1.6

Parameters for A/D Converter .............................................................................................................10

Table 1.7

Parameters for Analog Output (DAC and Buffer) ................................................................................10

Table 1.8

Parameters for ZACwire™ Serial Interface .........................................................................................10

Table 1.9

Parameters for System Response.......................................................................................................11

Table 1.10 ADC Resolution Characteristics for an Analog Gain of 6 ....................................................................11

Table 1.11 ADC Resolution Characteristics for an Analog Gain of 12 ..................................................................12

Table 1.12 ADC Resolution Characteristics for an Analog Gain of 24 ..................................................................12

Table 1.13 ADC Resolution Characteristics for an Analog Gain of 48 ..................................................................13

Table 2.1

Order of Trim Codes ............................................................................................................................19

Table 2.2

Oscillator Trimming..............................................................................................................................20

Table 3.1

Pin Configuration and Latch-Up Conditions ........................................................................................22

Table 3.2

Total Transmission Time for Different Update Rate Settings and Output Configuration.....................25

Table 3.3

Special Measurement versus Update Rate .........................................................................................26

Table 3.4

Command/Data Bytes Encoding..........................................................................................................27

Table 3.5

Programming Details for Command 30H..............................................................................................27

Table 3.6

ZSC31010 EEPROM Bits ....................................................................................................................30