1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

VM

DIN

CLK

LATCH

GND

DOUT

ENABLE

nFAULT

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8

DRV8860

www.ti.com

SLRS065A – SEPTEMBER 2013 – REVISED NOVEMBER 2013

PW (TSSOP) PACKAGE

(TOP VIEW)

Pin Functions

NAME

PIN

DESCRIPTION

EXTERNAL COMPONENTS OR CONNECTIONS

POWER AND GROUND

GND

5

—

Device ground

All pins must be connected to ground

Connect to motor supply voltage. Bypass to GND with a 0.1

μF ceramic capacitor

VM

1

—

Motor power supply

plus a 10

μF electrolytic capacitor.

CONTROL AND SERIAL INTERFACE

Output stage enable

Logic high to enable outputs, logic low to disable outputs. Internal logic and

ENABLE

8

I

control input

registers can be read and written to when ENABLE is logic low. Internal pulldown.

LATCH

4

I

Serial latch signal

Refer to serial communication waveforms. Internal pulldown.

Rising edge clocks data into part for write operations. Falling edge clocks data out

CLK

3

I

Serial clock input

of part for read operations. Internal pulldown.

DIN

2

I

Serial data input

Serial data input from controller. Internal pulldown.

DOUT

6

O

Serial data output

Serial data output to controller. Open-drain output with internal pullup.

STATUS

Logic low when in fault condition. Open-drain output requires external pullup.

nFAULT

7

OD

Fault

Faults: OCP, OL, OTS, UVLO

OUTPUT

OUT1

16

O

Low-side output 1

NFET output driver. Connect external load between this pin and VM

OUT2

15

O

Low-side output 2

NFET output driver. Connect external load between this pin and VM

OUT3

14

O

Low-side output 3

NFET output driver. Connect external load between this pin and VM

OUT4

13

O

Low-side output 4

NFET output driver. Connect external load between this pin and VM

OUT5

12

O

Low-side output 5

NFET output driver. Connect external load between this pin and VM

OUT6

11

O

Low-side output 6

NFET output driver. Connect external load between this pin and VM

OUT7

10

O

Low-side output 7

NFET output driver. Connect external load between this pin and VM

OUT8

9

O

Low-side output 8

NFET output driver. Connect external load between this pin and VM

(1)

Directions: I = input, O = output, OZ = tri-state output, OD = open-drain output, IO = input/output

Critical Components

PIN

NAME

COMPONENT

10µF electrolytic rated for VM voltage to GND,

1

VM

0.1µF ceramic rated for VM voltage to GND

7

nFAULT

Requires external pullup to logic supply

Copyright © 2013, Texas Instruments Incorporated

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