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DMVA3AAAR Datasheet(PDF) 1 Page - Texas Instruments |
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DMVA3AAAR Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 287 page  DMVA3, DMVA4 www.ti.com SPRS872B – MAY 2013 – REVISED DECEMBER 2013 DMVA3 and DMVA4 DaVinci™ Digital Media Processor Check for Samples: DMVA3 1 High-Performance System-on-Chip (SoC) 1.1 Features 1234 • High-Performance DaVinci Digital Media • Face Detect (FD) Engine Processors – Hardware Face Detection for up to 35 Faces – Up to 970-MHz ARM® Cortex™-A8 RISC Per Frame Processor • Programmable High-Definition Video Image – Up to 1940 ARM Cortex-A8 MIPS Coprocessing (HDVICP v2) Engine • ARM Cortex-A8 Core – Encode, Decode, Transcode Operations – ARMv7 Architecture – H.264 BP/MP/HP, MPEG-2, VC-1, MPEG-4 SP/ASP, JPEG/MJPEG • In-Order, Dual-Issue, Superscalar Processor Core – Fourth-Generation Motion-Compensated Noise Filter • NEON™ Multimedia Architecture • Media Controller • Supports Integer and Floating Point – Controls the HDVPSS, HDVICP2, Vision • Jazelle® RCT Execution Environment Coprocessor, and ISS • ARM Cortex-A8 Memory Architecture • Endianness – 32KB of Instruction and Data Caches – ARM Instructions and Data – Little Endian – 256KB of L2 Cache with ECC • HD Video Processing Subsystem (HDVPSS) – 64KB of RAM, 48KB of Boot ROM – Two 165-MHz HD Video Capture Inputs • 256KB of On-Chip Memory Controller (OCMC) • One 16- or 24-Bit Input, Splittable Into RAM Dual 8-Bit SD Capture Ports • Imaging Subsystem (ISS) • One 8-, 16-, or 24-Bit HD Input and 8-Bit – Camera Sensor Connection SD Input Capture Port • Parallel Connection for Raw (up to 16-Bit) – Two 165-MHz HD Video Display Outputs and BT.656/BT.1120 (8- or 16-Bit) • One 16-, 24-, or 30-Bit and One 16- or 24- • CSI2 Serial Connection Bit Output – Image Sensor Interface (ISIF) for Handling – Component HD Analog Output Image and Video Data From the Camera – Composite Analog Output Sensor – Digital HDMI 1.3 Transmitter with Integrated – Image Pipe Interface (IPIPEIF) for Image and PHY Video Data Connection Between Camera Sensor, ISIF, IPIPE, and DRAM – Advanced Video Processing Features Such as Scan, Format, and Rate Conversion – Image Pipe (IPIPE) for Real-Time Image and Video Processing – Three Graphics Layers and Compositors – Resizer • 32-Bit DDR2, DDR3, and DDR3L SDRAM Interface • Resizing Image and Video From 1/16x to 8x – Supports up to 400 MHz for DDR2, 533 MHz for DDR3, and 533 MHz for DDR3L • Generating Two Different Resizing Outputs Concurrently – Up to Two x 16 Devices, 2GB of Total Address Space • Hardware 3A Engine (H3A) for Generating Key Statistics for 3A (AE, AWB, and AF) – Dynamic Memory Manager (DMM) Control • Programmable Multi-Zone Memory • Vision Coprocessor Mapping • Enables Efficient 2D Block Accesses • Supports Tiled Objects in 0°, 90°, 180°, or 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 Device/BIOS, XDS are trademarks of Texas Instruments. 3 Skype is a trademark of Skype. 4 All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to Copyright © 2013, Texas Instruments Incorporated specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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