AD9681 datasheet(10/40 Pages) AD

Part #	AD9681

Description	Octal, 14-Bit, 125 MSPS, Serial LVDS, 1.8 V Analog-to-Digital Converter

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10 / 40 page

AD9681

Data Sheet

Rev. A | Page 10 of 40

D0–A1

D0+A1

D1–A1

D1+A1

FCO–1, FCO–2

BYTEWISE

MODE

FCO+1, FCO+2

D0–A1

D0+A1

D1–A1

D1+A1

FCO–1, FCO–2

DCO–1, DCO–2

DCO+1, DCO+2

CLK+

CLK–

DCO–1, DCO–2

FCO+1, FCO+2

BITWISE

MODE

SDR

DDR

D10

N – 16

D08

N – 16

D06

N – 16

D04

N – 16

D02

N – 16

LSB

N – 16

D10

N – 17

D08

N – 17

D06

N – 17

D04

N – 17

D02

N – 17

LSB

N – 17

MSB

N – 16

D09

N – 16

D07

N – 16

D05

N – 16

D03

N – 16

D01

N – 16

MSB

N – 17

D09

N – 17

D07

N – 17

D05

N – 17

D03

N – 17

D01

N – 17

D05

N – 16

D04

N – 16

D03

N – 16

D02

N – 16

D01

N – 16

LSB

N – 16

D05

N – 17

D04

N – 17

D03

N – 17

D02

N – 17

D01

N – 17

LSB

N – 17

MSB

N – 16

D10

N – 16

D09

N – 16

D08

N – 16

D07

N – 16

D06

N – 16

MSB

N – 17

D10

N – 17

D09

N – 17

D08

N – 17

D07

N – 17

D06

N – 17

tEH

tCPD

tFRAME

tFCO

tPD

tDATA

tLD

tEL

VIN±x1, VIN±x2

tA

N – 1

N

N + 1

Figure 6. 12-Bit DDR/SDR, Two-Lane, 2× Frame Mode

D0–x

D0+x

FCO–1, FCO–2

DCO+1, DCO+2

CLK+

VIN±x1, VIN±x2

CLK–

DCO–1, DCO–2

FCO+1, FCO+2

D12

N – 17

MSB

N – 17

D11

N – 17

D10

N – 17

D9

N – 17

D8

N – 17

D7

N – 17

D6

N – 17

D5

N – 17

D4

N – 17

D3

N – 17

D2

N – 17

D1

N – 17

LSB

N – 17

0

N – 17

0

N – 17

MSB

N – 16

D14

N – 16

D13

N – 16

tA

tDATA

tEH

tFCO

tFRAME

tPD

tCPD

tEL

N – 1

N

Figure 7. Wordwise DDR, One-Lane, 1× Frame, 16-Bit Output Mode

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